Patents by Inventor Mario Allegra
Mario Allegra has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11942183Abstract: Methods, systems, and devices for adaptive write operations for a memory device are described. In an example, the described techniques may include identifying a quantity of access operations performed on a memory array, modifying one or more parameters for a write operation based on the identified quantity of access operations, and writing logic states to the memory array by performing the write operation according to the one or more modified parameters. In some examples, the memory array may include memory cells associated with a configurable material element, such as a chalcogenide material, that stores a logic state based on a material property of the material element. In some examples, the described techniques may at least partially compensate for a change in memory material properties due to aging or other degradation or changes over time (e.g., due to accumulated access operations).Type: GrantFiled: October 15, 2021Date of Patent: March 26, 2024Assignee: Micron Technology, Inc.Inventors: Mattia Boniardi, Richard K. Dodge, Innocenzo Tortorelli, Mattia Robustelli, Mario Allegra
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Patent number: 11837267Abstract: Methods, systems, devices, and other implementations to store fuse data in memory devices are described. Some implementations may include an array of memory cells with different portions of cells for storing data. A first portion of the array may store fuse data and may contain a chalcogenide storage element, while a second portion of the array may store user data. Sense circuitry may be coupled with the array, and may determine the value of the fuse data using various signaling techniques. In some cases, the sense circuitry may implement differential storage and differential signaling to determine the value of the fuse data stored in the first portion of the array.Type: GrantFiled: May 20, 2021Date of Patent: December 5, 2023Assignee: Micron Technology, Inc.Inventors: Mattia Boniardi, Anna Maria Conti, Mattia Robustelli, Innocenzo Tortorelli, Mario Allegra
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Patent number: 11763886Abstract: Methods, systems, and devices related to techniques to access a self-selecting memory device are described. A self-selecting memory cell may store one or more bits of data represented by different threshold voltages of the self-selecting memory cell. A programming pulse may be varied to establish the different threshold voltages by modifying one or more time durations during which a fixed level of voltage or current is maintained across the self-selecting memory cell. The self-selecting memory cell may include a chalcogenide alloy. A non-uniform distribution of an element in the chalcogenide alloy may determine a particular threshold voltage of the self-selecting memory cell. The shape of the programming pulse may be configured to modify a distribution of the element in the chalcogenide alloy based on a desired logic state of the self-selecting memory cell.Type: GrantFiled: October 12, 2021Date of Patent: September 19, 2023Assignee: Micron Technology, Inc.Inventors: Innocenzo Tortorelli, Andrea Redaelli, Agostino Pirovano, Fabio Pellizzer, Mario Allegra, Paolo Fantini
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Publication number: 20230240160Abstract: A phase-change memory cell includes a heater, a memory region made of a phase-change material located above said heater, and an electrically conductive element positioned adjacent to the memory region and the heater at a first side of the heater. The electrically conductive element extends parallel to a first axis and has, parallel to the first axis, a first dimension at the first side that is greater than a second dimension at a second side opposite to the first side.Type: ApplicationFiled: January 20, 2023Publication date: July 27, 2023Applicant: STMicroelectronics S.r.l.Inventors: Mario ALLEGRA, Andrea REDAELLI
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Publication number: 20220115068Abstract: Methods, systems, and devices related to techniques to access a self-selecting memory device are described. A self-selecting memory cell may store one or more bits of data represented by different threshold voltages of the self-selecting memory cell. A programming pulse may be varied to establish the different threshold voltages by modifying one or more time durations during which a fixed level of voltage or current is maintained across the self-selecting memory cell. The self-selecting memory cell may include a chalcogenide alloy. A non-uniform distribution of an element in the chalcogenide alloy may determine a particular threshold voltage of the self-selecting memory cell. The shape of the programming pulse may be configured to modify a distribution of the element in the chalcogenide alloy based on a desired logic state of the self-selecting memory cell.Type: ApplicationFiled: October 12, 2021Publication date: April 14, 2022Inventors: Innocenzo Tortorelli, Andrea Redaelli, Agostino Pirovano, Fabio Pellizzer, Mario Allegra, Paolo Fantini
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Publication number: 20220108732Abstract: Methods, systems, and devices for adaptive write operations for a memory device are described. In an example, the described techniques may include identifying a quantity of access operations performed on a memory array, modifying one or more parameters for a write operation based on the identified quantity of access operations, and writing logic states to the memory array by performing the write operation according to the one or more modified parameters. In some examples, the memory array may include memory cells associated with a configurable material element, such as a chalcogenide material, that stores a logic state based on a material property of the material element. In some examples, the described techniques may at least partially compensate for a change in memory material properties due to aging or other degradation or changes over time (e.g., due to accumulated access operations).Type: ApplicationFiled: October 15, 2021Publication date: April 7, 2022Inventors: Mattia Boniardi, Richard K. Dodge, Innocenzo Tortorelli, Mattia Robustelli, Mario Allegra
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Patent number: 11283016Abstract: A memory cell can include a chalcogenide material configured in an annular shape or a chalcogenide material substantially circumscribing an interior conductive channel. Such memory cells can be included in memory structures having an interior conductive channel and a plurality of alternating dielectric layers and memory layers oriented along the interior conductive channel. Individual memory layers can include a chalcogenide material substantially circumscribing the interior conductive channel.Type: GrantFiled: August 28, 2020Date of Patent: March 22, 2022Assignee: Intel CorporationInventor: Mario Allegra
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Patent number: 11158358Abstract: Methods, systems, and devices for adaptive write operations for a memory device are described. In an example, the described techniques may include identifying a quantity of access operations performed on a memory array, modifying one or more parameters for a write operation based on the identified quantity of access operations, and writing logic states to the memory array by performing the write operation according to the one or more modified parameters. In some examples, the memory array may include memory cells associated with a configurable material element, such as a chalcogenide material, that stores a logic state based on a material property of the material element. In some examples, the described techniques may at least partially compensate for a change in memory material properties due to aging or other degradation or changes over time (e.g., due to accumulated access operations).Type: GrantFiled: July 22, 2019Date of Patent: October 26, 2021Assignee: Micron Technology, Inc.Inventors: Mattia Boniardi, Richard K. Dodge, Innocenzo Tortorelli, Mattia Robustelli, Mario Allegra
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Patent number: 11152065Abstract: Methods, systems, and devices related to techniques to access a self-selecting memory device are described. A self-selecting memory cell may store one or more bits of data represented by different threshold voltages of the self-selecting memory cell. A programming pulse may be varied to establish the different threshold voltages by modifying one or more time durations during which a fixed level of voltage or current is maintained across the self-selecting memory cell. The self-selecting memory cell may include a chalcogenide alloy. A non-uniform distribution of an element in the chalcogenide alloy may determine a particular threshold voltage of the self-selecting memory cell. The shape of the programming pulse may be configured to modify a distribution of the element in the chalcogenide alloy based on a desired logic state of the self-selecting memory cell.Type: GrantFiled: April 30, 2020Date of Patent: October 19, 2021Assignee: Micron Technology, Inc.Inventors: Innocenzo Tortorelli, Andrea Redaelli, Agostino Pirovano, Fabio Pellizzer, Mario Allegra, Paolo Fantini
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Patent number: 11114159Abstract: In an example, a first data structure can be read with a first read voltage dedicated to the first data structure. A second data structure that stores a larger quantity of data than the first data structure can be with a second read voltage that is dedicated to the second data structure. The first data structure can be with a third read voltage in response to a quantity of errors in reading the first data structure being greater than or equal to a first threshold quantity. The second data structure can be read with the third read voltage in response to a quantity of errors in reading the second data structure being greater than or equal to a second threshold quantity. The read voltages can be based on a temperature of an apparatus that includes the first and second data structures.Type: GrantFiled: May 18, 2020Date of Patent: September 7, 2021Assignee: Micron Technology, Inc.Inventors: Marco Sforzin, Mattia Robustelli, Innocenzo Tortorelli, Mario Allegra, Paolo Amato
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Publication number: 20210272615Abstract: Methods, systems, devices, and other implementations to store fuse data in memory devices are described. Some implementations may include an array of memory cells with different portions of cells for storing data. A first portion of the array may store fuse data and may contain a chalcogenide storage element, while a second portion of the array may store user data. Sense circuitry may be coupled with the array, and may determine the value of the fuse data using various signaling techniques. In some cases, the sense circuitry may implement differential storage and differential signaling to determine the value of the fuse data stored in the first portion of the array.Type: ApplicationFiled: May 20, 2021Publication date: September 2, 2021Inventors: Mattia Boniardi, Anna Maria Conti, Mattia Robustelli, Innocenzo Tortorelli, Mario Allegra
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Patent number: 11037613Abstract: Methods, systems, devices, and other implementations to store fuse data in memory devices are described. Some implementations may include an array of memory cells with different portions of cells for storing data. A first portion of the array may store fuse data and may contain a chalcogenide storage element, while a second portion of the array may store user data. Sense circuitry may be coupled with the array, and may determine the value of the fuse data using various signaling techniques. In some cases, the sense circuitry may implement differential storage and differential signaling to determine the value of the fuse data stored in the first portion of the array.Type: GrantFiled: July 17, 2019Date of Patent: June 15, 2021Assignee: Micron Technology, Inc.Inventors: Mattia Boniardi, Anna Maria Conti, Mattia Robustelli, Innocenzo Tortorelli, Mario Allegra
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Publication number: 20210050519Abstract: A memory cell can include a chalcogenide material configured in an annular shape or a chalcogenide material substantially circumscribing an interior conductive channel. Such memory cells can be included in memory structures having an interior conductive channel and a plurality of alternating dielectric layers and memory layers oriented along the interior conductive channel. Individual memory layers can include a chalcogenide material substantially circumscribing the interior conductive channel.Type: ApplicationFiled: August 28, 2020Publication date: February 18, 2021Applicant: Intel CorporationInventor: Mario Allegra
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Publication number: 20210027813Abstract: Methods, systems, and devices for adaptive write operations for a memory device are described. In an example, the described techniques may include identifying a quantity of access operations performed on a memory array, modifying one or more parameters for a write operation based on the identified quantity of access operations, and writing logic states to the memory array by performing the write operation according to the one or more modified parameters. In some examples, the memory array may include memory cells associated with a configurable material element, such as a chalcogenide material, that stores a logic state based on a material property of the material element. In some examples, the described techniques may at least partially compensate for a change in memory material properties due to aging or other degradation or changes over time (e.g., due to accumulated access operations).Type: ApplicationFiled: July 22, 2019Publication date: January 28, 2021Inventors: Mattia Boniardi, Richard K. Dodge, Innocenzo Tortorelli, Mattia Robustelli, Mario Allegra
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Publication number: 20210020218Abstract: Methods, systems, devices, and other implementations to store fuse data in memory devices are described. Some implementations may include an array of memory cells with different portions of cells for storing data. A first portion of the array may store fuse data and may contain a chalcogenide storage element, while a second portion of the array may store user data. Sense circuitry may be coupled with the array, and may determine the value of the fuse data using various signaling techniques. In some cases, the sense circuitry may implement differential storage and differential signaling to determine the value of the fuse data stored in the first portion of the array.Type: ApplicationFiled: July 17, 2019Publication date: January 21, 2021Inventors: Mattia Boniardi, Anna Maria Conti, Mattia Robustelli, Innocenzo Tortorelli, Mario Allegra
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Publication number: 20200327940Abstract: Methods, systems, and devices related to techniques to access a self-selecting memory device are described. A self-selecting memory cell may store one or more bits of data represented by different threshold voltages of the self-selecting memory cell. A programming pulse may be varied to establish the different threshold voltages by modifying one or more time durations during which a fixed level of voltage or current is maintained across the self-selecting memory cell. The self-selecting memory cell may include a chalcogenide alloy. A non-uniform distribution of an element in the chalcogenide alloy may determine a particular threshold voltage of the self-selecting memory cell. The shape of the programming pulse may be configured to modify a distribution of the element in the chalcogenide alloy based on a desired logic state of the self-selecting memory cell.Type: ApplicationFiled: April 30, 2020Publication date: October 15, 2020Inventors: Innocenzo Tortorelli, Andrea Redaelli, Agostino Pirovano, Fabio Pellizzer, Mario Allegra, Paolo Fantini
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Publication number: 20200279604Abstract: In an example, a first data structure can be read with a first read voltage dedicated to the first data structure. A second data structure that stores a larger quantity of data than the first data structure can be with a second read voltage that is dedicated to the second data structure. The first data structure can be with a third read voltage in response to a quantity of errors in reading the first data structure being greater than or equal to a first threshold quantity. The second data structure can be read with the third read voltage in response to a quantity of errors in reading the second data structure being greater than or equal to a second threshold quantity. The read voltages can be based on a temperature of an apparatus that includes the first and second data structures.Type: ApplicationFiled: May 18, 2020Publication date: September 3, 2020Inventors: Marco Sforzin, Mattia Robustelli, Innocenzo Tortorelli, Mario Allegra, Paolo Amato
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Patent number: 10763432Abstract: A memory cell can include a chalcogenide material configured in an annular shape or a chalcogenide material substantially circumscribing an interior conductive channel. Such memory cells can be included in memory structures having an interior conductive channel and a plurality of alternating dielectric layers and memory layers oriented along the interior conductive channel. Individual memory layers can include a chalcogenide material substantially circumscribing the interior conductive channel.Type: GrantFiled: December 13, 2018Date of Patent: September 1, 2020Assignee: Intel CorporationInventor: Mario Allegra
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Patent number: 10714177Abstract: Methods, systems, and devices for operating and forming a multilevel memory cell and array are described. A multilevel memory cell includes two or more binary memory elements, which may include phase change material. Each memory element may be programmed to one of two possible states—e.g., a fully amorphous state or a fully crystalline state. By combining multiple binary memory elements in a single memory cell, the memory cell may be programmed to store more than two states. The different memory elements may be programmed by selectively melting each memory element. Selective melting may be controlled by using memory elements with different melting temperatures or using electrodes with different electrical resistances, or both.Type: GrantFiled: April 17, 2019Date of Patent: July 14, 2020Assignee: Micron Technology, Inc.Inventors: Mario Allegra, Mattia Boniardi
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Publication number: 20200194670Abstract: A memory cell can include a chalcogenide material configured in an annular shape or a chalcogenide material substantially circumscribing an interior conductive channel. Such memory cells can be included in memory structures having an interior conductive channel and a plurality of alternating dielectric layers and memory layers oriented along the interior conductive channel. Individual memory layers can include a chalcogenide material substantially circumscribing the interior conductive channel.Type: ApplicationFiled: December 13, 2018Publication date: June 18, 2020Applicant: Intel CorporationInventor: Mario Allegra