Abstract: A self-luminous display panel 10 in which self-luminous elements 2 are arranged on a plane, wherein each of the self-luminous elements includes: a pair of electrodes 13, 20 disposed facing each other, an electrode of the pair of electrodes including a metal layer 20A; functional layers 15, 16, 17, 18, 19 including a light emitting layer 17, disposed between the pair of electrodes; and a sealing layer 21 that covers the pair of electrodes and the functional layers from a direction. The self-luminous elements include a repaired self-luminous element 2?. The repaired self-luminous element includes a foreign object FO among the functional layers. The electrode including the metal layer has a high resistance portion 201 surrounding, in plan view, an area containing the foreign object, and has a thickened portion 202 of the metal layer at an outer edge, in plan view, of the high resistance portion.

Abstract: A self-luminous display panel 10 in which self-luminous elements 2 are arranged on a plane, wherein each of the self-luminous elements includes: a pair of electrodes 13, 20 disposed facing each other, an electrode of the pair of electrodes including a metal layer 20A; functional layers 15, 16, 17, 18, 19 including a light emitting layer 17, disposed between the pair of electrodes; and a sealing layer 21 that covers the pair of electrodes and the functional layers from a direction. The self-luminous elements include a repaired self-luminous element 2?. The repaired self-luminous element includes a foreign object FO among the functional layers. The electrode including the metal layer has a high resistance portion 201 surrounding, in plan view, an area containing the foreign object, and has a thickened portion 202 of the metal layer at an outer edge, in plan view, of the high resistance portion.

Abstract: A method for manufacturing a display panel including a display unit in which pixels, in rows and columns, include an organic EL element and a drive transistor, includes, performed on the display panel having a line defect which is a pixel column that emits light of luminance not reflecting display gray level signals: displaying, overlappingly, a lighted line, which is a pixel column inputted with uniform display gray level signals, and the line defect by displaying the lighted line on the display unit and scanning the display unit with the lighted line in the row direction; reducing a bright/dark part range in the line defect by uniformly changing the display gray level inputted to the pixel column in the lighted line overlapping with the line defect; and identifying a defective pixel, which is the line defect origin, from the position of the reduced bright/dark part range in the display unit.

Abstract: A method for manufacturing a display panel including a display unit in which pixels, in rows and columns, include an organic EL element and a drive transistor, includes, performed on the display panel having a line defect which is a pixel column that emits light of luminance not reflecting display gray level signals: displaying, overlappingly, a lighted line, which is a pixel column inputted with uniform display gray level signals, and the line defect by displaying the lighted line on the display unit and scanning the display unit with the lighted line in the row direction; reducing a bright/dark part range in the line defect by uniformly changing the display gray level inputted to the pixel column in the lighted line overlapping with the line defect; and identifying a defective pixel, which is the line defect origin, from the position of the reduced bright/dark part range in the display unit.

Abstract: Each of the column electrodes is divided into an upper electrode portion and a lower electrode portion. The panel surface is made up of an upper panel face facing the upper electrode portion and a lower panel face facing the lower electrode portion. A transverse wall of the partition wall unit is disposed facing the boundary area between the upper and lower panel faces. The upper and lower electrode portions of the column electrode have the opposing ends at which projections are respectively provided and extend out toward the respective other electrode portions.

Abstract: A crystalline magnesium oxide layer, including magnesium oxide crystals causing a cathode-luminescence emission having a peak within a wavelength range of 200 nm to 300 nm upon excitation by an electron beam, is provided between the front glass substrate and the back glass substrate, facing the discharge cells. The phosphor layer of any one of red, green and blue colors has a discharge timing adjusting function for giving rise to an approximate match between a timing of a discharge initiated in the green discharge cell and a timing of a discharge initiated in the red or blue discharge cell.

Abstract: Each of the column electrodes is divided into an upper electrode portion and a lower electrode portion. The panel surface is made up of an upper panel face facing the upper electrode portion and a lower panel face facing the lower electrode portion. A transverse wall of the partition wall unit is disposed facing the boundary area between the upper and lower panel faces. The upper and lower electrode portions of the column electrode have the opposing ends at which projections are respectively provided and extend out toward the respective other electrode portions.

Abstract: A plasma display panel comprises a plurality of row electrode pairs (X, Y) and a dielectric layer 12 covering the row electrode pairs (X, Y) provided on a front glass substrate 10, and also column electrodes D provided on a back glass substrate 13 to intersect with the row electrode pairs (X, Y) so as to form display discharge cells C1 in a discharge space at the intersections. A discharge area C2 is formed between the adjacent display discharge cells C1 in the column direction to provide for a discharge created between the back to back row electrodes X and Y of the adjacent row electrode pairs (X, Y). A recess groove 12A is formed in a portion of the dielectric layer 12 opposite each discharge area C2.

Abstract: A crystalline magnesium oxide layer, including magnesium oxide crystals causing a cathode-luminescence emission having a peak within a wavelength range of 200 nm to 300 nm upon excitation by an electron beam, is provided between the front glass substrate and the back glass substrate, facing the discharge cells. The phosphor layer of any one of red, green and blue colors has a discharge timing adjusting function for giving rise to an approximate match between a timing of a discharge initiated in the green discharge cell and a timing of a discharge initiated in the red or blue discharge cell.

Abstract: An object of the present invention is to provide a high definition PDP screen without lowering the PDP luminescence efficiency. The display panel is provided with a plurality of cells that are arranged in a matrix, each of the plurality of cells emitting a different unique luminescent color; wherein a plurality of cells each bearing first luminescent color are disposed on every other line in a vertical direction, and a line of cells each having second luminescent color and a line of cells each having third luminescent color are alternated with a line of said plurality of cells having first luminescent color respectively therebetween.

Abstract: A plasma display panel comprises a front glass substrate and a back glass substrate. A plurality of row electrode pairs regularly arranged in a column direction, each extending in a row direction to form a display line, and a dielectric layer covering the row electrode pairs are provided on an inner surface of the substrate. A plurality of column electrodes are provided on an inner surface of the substrate, and regularly arranged in the row direction, each extending in the column direction to intersect with the row electrode pairs to form discharge cells in a discharge space at the intersections. A recess groove is formed in a portion of the dielectric layer opposite a discharge gap between paired row electrodes constituting the row electrode pair, so that the dielectric layer has a thickness in the portion opposite the discharge gap smaller than that in portions on both sides of the portion opposite the discharge gap.

Abstract: A recessed groove h is formed in a portion of an inner surface of a front glass substrate 10 facing a non-display area between adjacent discharge cells C in a column direction. Each of adjacent bus electrodes Xb and Yb of the respective row electrodes X and Y positioned back to back in between the adjacent row electrode pairs (X, Y) is formed to extend along the corresponding side face of the two side faces of the recessed groove h in such a way as to raise the bus electrode in relation to the corresponding transparent electrode Xa or Ya in a thickness direction of the front glass substrate 10.

Abstract: A plasma display panel comprises a front glass substrate 1 and a back glass substrate 4. A plurality of row electrode pairs (X, Y) regularly arranged in a column direction, each extending in a row direction to form a display line, and a dielectric layer 2 covering the row electrode pairs (X, Y) are provided on an inner surface of the substrate 1. A plurality of column electrodes D are provided on an inner surface of the substrate 4, and regularly arranged in the row direction, each extending in the column direction to intersect with the row electrode pairs (X, Y) to form discharge cells C in a discharge space at the intersections. A recess groove 12a is formed in a portion of the dielectric layer 2 opposite a discharge gap g between paired row electrodes X and Y constituting the row electrode pair (X, Y), so that the dielectric layer 2 has a thickness in the portion opposite the discharge gap g smaller than that in portions on both sides of the portion opposite the discharge gap g.

Abstract: A plasma display panel includes a front glass substrate 1 having the back surface on which a plurality of pairs of row electrodes X1, Y1 are formed, a back glass substrate 4 on which column electrodes D are formed, and partition walls 6 made of dielectric materials and defining individual discharge cells C, in which at least either of the row electrodes X1 and Y1 is placed at a position shifted relatively in the column direction toward decreasing the overlapping of the row electrode and the partition wall in reference to the partition wall 6.

Abstract: A plasma display panel (10) includes a front glass substrate (11) having the inner face on which row electrode pairs (X, Y) each opposing each other through a discharge gap (g) and a dielectric layer (13) overlaying the row electrode pairs (X, Y) relative to a discharge space (S). In such plasma display panel (10), a low dielectric constant layer (12) having a relative dielectric constant lower than that of the front glass substrate (11) is provided between the front glass substrate (11) and the row electrode pair (X, Y).

Abstract: A plasma display panel comprises a plurality of row electrode pairs (X, Y) and a dielectric layer 12 covering the row electrode pairs (X, Y) provided on a front glass substrate 10, and also column electrodes D provided on a back glass substrate 13 to intersect with the row electrode pairs (X, Y) so as to form display discharge cells C1 in a discharge space at the intersections. A discharge area C2 is formed between the adjacent display discharge cells C1 in the column direction to provide for a discharge created between the back to back row electrodes X and Y of the adjacent row electrode pairs (X, Y). A recess groove 12A is formed in a portion of the dielectric layer 12 opposite each discharge area C2.

Abstract: A recessed groove h is formed in a portion of an inner surface of a front glass substrate 10 facing a non-display area between adjacent discharge cells C in a column direction. Each of adjacent bus electrodes Xb and Yb of the respective row electrodes X and Y positioned back to back in between the adjacent row electrode pairs (X, Y) is formed to extend along the corresponding side face of the two side faces of the recessed groove h in such a way as to raise the bus electrode in relation to the corresponding transparent electrode Xa or Ya in a thickness direction of the front glass substrate 10.

Abstract: An object of the present invention is to provide a high definition PDP screen without lowering the PDP luminescence efficiency.

Abstract: A plasma display panel includes a front glass substrate 1 having the back surface on which a plurality of pairs of row electrodes X1, Y1 are formed, a back glass substrate 4 on which column electrodes D are formed, and partition walls 6 made of dielectric materials and defining individual discharge cells C, in which at least either of the row electrodes X1 and Y1 is placed at a position shifted relatively in the column direction toward decreasing the overlapping of the row electrode and the partition wall in reference to the partition wall 6.

Abstract: A plasma display panel (10) includes a front glass substrate (11) having the inner face on which row electrode pairs (X, Y) each opposing each other through a discharge gap (g) and a dielectric layer (13) overlaying the row electrode pairs (X, Y) relative to a discharge space (S). In such plasma display panel (10), a low dielectric constant layer (12) having a relative dielectric constant lower than that of the front glass substrate (11) is provided between the front glass substrate (11) and the row electrode pair (X, Y).