Patents by Inventor Mario Blaum
Mario Blaum has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11928497Abstract: A computer-implemented method according to one embodiment includes receiving a request to perform a transaction in persistent memory at a first node; implementing the transaction within a volatile transaction cache at the first node; determining parity data for the transaction at the first node; sending the parity data from the first node to a parity node; and transferring results of the transaction from the volatile transaction cache to the persistent memory at the first node.Type: GrantFiled: January 27, 2020Date of Patent: March 12, 2024Assignee: International Business Machines CorporationInventors: Daniel Waddington, Mario Blaum
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Patent number: 11474898Abstract: A computer implemented method for recovering erased entries within a system of arrays includes identifying a system consisting of a plurality of arrays, wherein each array consists of m rows and n columns of entries, each entry is divided into p symbols consisting of a plurality of bits, protecting the m rows and n columns of entries in the system with an erasure-correcting code allowing the recovery of a number of erased entries in such rows and columns, detecting an erasure corresponding to an entry in the identified system, and, responsive to detecting an erasure, determining the value of the erased entry according to the p symbols of one or more non-erased entries.Type: GrantFiled: December 9, 2020Date of Patent: October 18, 2022Assignee: International Business Machines CorporationInventors: Mario Blaum, Steven Robert Hetzler
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Publication number: 20220179739Abstract: A computer implemented method for recovering erased entries within a system of arrays includes identifying a system consisting of a plurality of arrays, wherein each array consists of m rows and n columns of entries, each entry is divided into p symbols consisting of a plurality of bits, protecting the m rows and n columns of entries in the system with an erasure-correcting code allowing the recovery of a number of erased entries in such rows and columns, detecting an erasure corresponding to an entry in the identified system, and, responsive to detecting an erasure, determining the value of the erased entry according to the p symbols of one or more non-erased entries.Type: ApplicationFiled: December 9, 2020Publication date: June 9, 2022Inventors: Mario Blaum, Steven Robert Hetzler
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Patent number: 11190209Abstract: A computer-implemented method includes encoding an array of (p?1)×k symbols of data into a p×(k+r) array. The method includes p is a prime number, r?1, and k?p?r. The method also includes each column in the p×(k+r) array has an even parity and each line of slope j for 0?j?r?1 in the p×(k+r) array has an even parity. The method includes the lines of slope j taken with a toroidal topology modulo p. A computer program product for encoding an array of (p?1)×k symbols of data into a p×(k+r) array includes a computer readable storage medium having program instructions executable by a computer. The program instructions cause the computer to perform the foregoing method.Type: GrantFiled: January 30, 2019Date of Patent: November 30, 2021Assignee: International Business Machines CorporationInventors: Mario Blaum, Steven R. Hetzler, Veera W. Deenadhayalan
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Patent number: 11182249Abstract: A data storage system includes a plurality of data blocks. A set of data blocks are protected by an erasure correcting code and each of the data blocks in the set of data blocks includes block identification information. The data storage system includes a processor and logic integrated with the processor, executable by the processor, or integrated with and executable by the processor. The logic is configured to verify the block identification information for each of the data blocks in the set of data blocks at the time of read and, as part of reconstructing a data block, reconstruct the block identification information for the reconstructed data block, and verify the block identification information.Type: GrantFiled: June 24, 2020Date of Patent: November 23, 2021Assignee: International Business Machines CorporationInventors: Mario Blaum, Steven Robert Hetzler
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Publication number: 20210232421Abstract: A computer-implemented method according to one embodiment includes receiving a request to perform a transaction in persistent memory at a first node; implementing the transaction within a volatile transaction cache at the first node; determining parity data for the transaction at the first node; sending the parity data from the first node to a parity node; and transferring results of the transaction from the volatile transaction cache to the persistent memory at the first node.Type: ApplicationFiled: January 27, 2020Publication date: July 29, 2021Inventors: Daniel Waddington, Mario Blaum
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Patent number: 11038533Abstract: A computer-implemented method includes encoding an array of (p?1)×k symbols of data into a p×(k+r) array. The method includes p is a prime number, r?1, and k?p. The method includes each column in the p×(k+r) array has an even parity and symbol i in column r+j, for 0?i?p?1 and 0?j?r?1, is the XOR of symbols in a line of slope j taken with a toroidal topology modulo p in the k columns starting in symbol i of column 0.Type: GrantFiled: April 25, 2019Date of Patent: June 15, 2021Assignee: International Business Machines CorporationInventors: Mario Blaum, Steven R. Hetzler
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Publication number: 20200343914Abstract: A computer-implemented method includes encoding an array of (p?1)×k symbols of data into a p×(k+r) array. The method includes p is a prime number, r?1, and k?p. The method includes each column in the p×(k+r) array has an even parity and symbol i in column r+j, for 0?i?p?1 and 0?j?r?1, is the XOR of symbols in a line of slope j taken with a toroidal topology modulo p in the k columns starting in symbol i of column 0.Type: ApplicationFiled: April 25, 2019Publication date: October 29, 2020Inventors: Mario Blaum, Steven R. Hetzler
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Patent number: 10740182Abstract: A method for memory page erasure-correcting property generation in a storage array includes dividing data into multiple stripes for storage in a storage array including multiple storage devices with a topology of a hypercube of a dimension t?3. The storage devices in same hypercubes of dimension t?1 including the hypercube of dimension t have even parity. An intersection of two non-parallel planes in the hypercube topology is a line, and each point along a line is a storage device in the storage array. Erasure-correcting properties are generated for the data using three nested codes, wherein a first nested code has even parity over planes of class 0, 1 and 2, a second nested code has a first global parity, and a third nested code has a second global parity and a third global parity.Type: GrantFiled: December 20, 2018Date of Patent: August 11, 2020Assignee: International Business Machines CorporationInventors: Mario Blaum, Aayush Gupta, James Hafner, Steven R. Hetzler
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Patent number: 10740183Abstract: A computer-implemented method enables reconstructing contents of blocks in a storage system having l availability zones (AZs), a set of n storage units in each AZ arranged as columns, and a set of m storage blocks in each storage unit. The storage blocks of n+1 of the storage units are parity blocks, where l?1 of the AZs each include an additional parity block. The method includes using the parity blocks and/or data in the AZs and reconstructing contents of blocks in the storage system having l availability zones (AZs) from a concurrent loss of: one of the AZs, a storage unit together with one storage block in one of the remaining l?1 AZs, and one further storage block in each of the remaining l?2 AZs of the storage system.Type: GrantFiled: April 1, 2019Date of Patent: August 11, 2020Assignee: International Business Machines CorporationInventors: Mario Blaum, Steven R. Hetzler
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Publication number: 20200244284Abstract: A computer-implemented method includes encoding an array of (p?1)×k symbols of data into a p×(k+r) array. The method includes p is a prime number, r?1, and k?p?r. The method also includes each column in the p×(k+r) array has an even parity and each line of slope j for 0?j?r?1 in the p×(k+r) array has an even parity. The method includes the lines of slope j taken with a toroidal topology modulo p. A computer program product for encoding an array of (p?1)×k symbols of data into a p×(k+r) array includes a computer readable storage medium having program instructions executable by a computer. The program instructions cause the computer to perform the foregoing method.Type: ApplicationFiled: January 30, 2019Publication date: July 30, 2020Inventors: Mario Blaum, Steven R. Hetzler, Veera W. Deenadhayalan
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Patent number: 10620831Abstract: A controller including an object aggregator process that combines multiple data objects into a data segment, and transfers the data segment with reduced location metadata to storage media of at least one of multiple storage units. An erasure coder process generates code to encode the data segment into an erasure code that protects against concurrent data loss in the multiple storage units based on data reconstruction using a first responder, a second responder and a last responder.Type: GrantFiled: March 29, 2018Date of Patent: April 14, 2020Assignee: International Business Machines CorporationInventors: Mario Blaum, Steven R. Hetzler, Wayne C. Hineman, Robert M. Rees
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Patent number: 10572345Abstract: Embodiments relate to correcting erasures in a storage array. An aspect includes dividing data into a plurality of stripes for storage in a storage array comprising a plurality of storage locations, each stripe comprising M rows and N columns, each of the M rows including a number r of row parities, wherein r is greater than zero. Another aspect includes dividing each stripe into two or more column sets, each column set comprising a respective set of one or more columns of the stripe. Another aspect includes adding a respective first responder parity to each column set, wherein each first responder parity gives parity information for only the two or more columns in the first responder parity's respective column set.Type: GrantFiled: November 21, 2017Date of Patent: February 25, 2020Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Mario Blaum, Steven R. Hetzler
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Patent number: 10430123Abstract: A method includes distributively encoding data stored in a storage system using an erasure-correcting code. The encoded data is distributed into multiple w storage device arrays in the storage system. Each storage device array includes n storage devices. Each storage device is divided into m sectors or pages. The n storage devices are grouped into l groups of t storage devices each. Data erasures in the w storage device arrays are corrected by recovering erased data using the erasure-correcting code of un-erased data based on each row and column in each m×n array being protected by the erasure-correcting code for the data. Each group of t storage devices contains extra second responder parities to correct extra data erasures in addition to data erasures corrected by first responder vertical parities in each m×t subarray, and w, n, m, l and t are positive integers.Type: GrantFiled: April 30, 2018Date of Patent: October 1, 2019Assignee: International Business Machines CorporationInventors: John S. Best, Mario Blaum, Steven R. Hetzler
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Publication number: 20190171523Abstract: A method for memory page erasure-correcting property generation in a storage array includes dividing data into multiple stripes for storage in a storage array including multiple storage devices with a topology of a hypercube of a dimension t?3. The storage devices in same hypercubes of dimension t?1 including the hypercube of dimension t have even parity. An intersection of two non-parallel planes in the hypercube topology is a line, and each point along a line is a storage device in the storage array. Erasure-correcting properties are generated for the data using three nested codes, wherein a first nested code has even parity over planes of class 0, 1 and 2, a second nested code has a first global parity, and a third nested code has a second global parity and a third global parity.Type: ApplicationFiled: December 20, 2018Publication date: June 6, 2019Inventors: Mario Blaum, Aayush Gupta, James Hafner, Steven R. Hetzler
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Patent number: 10305516Abstract: Embodiments relate to a system with multiple erasure codes, and selecting and encoding for a write file with one of the codes to mitigate costs associated with storage recovery. The codes include a fast recovery code for frequently accessed data and a higher storage efficiency code for less frequently accessed data. State data is tracked to ascertain frequency of access to the file. One of the erasure codes is dynamically selected based on the tracked data, with the focus of the code select to lower recovery costs, and the data is encoded with the selected erasure code. Accordingly, the original coding of the write file is subject to change based on the tracked state data.Type: GrantFiled: August 1, 2016Date of Patent: May 28, 2019Assignee: International Business Machines CorporationInventors: Mario Blaum, James L. Hafner, David A. Pease, Mohit Saxena, Mingyuan Xia
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Patent number: 10241862Abstract: A method for memory page erasure reconstruction in a storage array includes dividing data into multiple stripes for storage in a storage array including multiple storage devices with a topology of a hypercube of a dimension t?3. The storage devices in same hypercubes of dimension t?1 including the hypercube of dimension t have even parity. An intersection of two non-parallel planes in the hypercube topology is a line, and each point along a line is a storage device in the storage array. A reconstructor processor reconstructs erased data for erased memory pages from non-erased data in the storage array by using parities in at least three dimensions based on the hypercube topology of the storage devices.Type: GrantFiled: May 17, 2018Date of Patent: March 26, 2019Assignee: International Business Machines CorporationInventors: Mario Blaum, Aayush Gupta, James Hafner, Steven R. Hetzler
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Publication number: 20180267857Abstract: A method for memory page erasure reconstruction in a storage array includes dividing data into multiple stripes for storage in a storage array including multiple storage devices with a topology of a hypercube of a dimension t?3. The storage devices in same hypercubes of dimension t?1 including the hypercube of dimension t have even parity. An intersection of two non-parallel planes in the hypercube topology is a line, and each point along a line is a storage device in the storage array. A reconstructor processor reconstructs erased data for erased memory pages from non-erased data in the storage array by using parities in at least three dimensions based on the hypercube topology of the storage devices.Type: ApplicationFiled: May 17, 2018Publication date: September 20, 2018Inventors: Mario Blaum, Aayush Gupta, James Hafner, Steven R. Hetzler
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Publication number: 20180246679Abstract: A method includes distributively encoding data stored in a storage system using an erasure-correcting code. The encoded data is distributed into multiple w storage device arrays in the storage system. Each storage device array includes n storage devices. Each storage device is divided into m sectors or pages. The n storage devices are grouped into l groups of t storage devices each. Data erasures in the w storage device arrays are corrected by recovering erased data using the erasure-correcting code of un-erased data based on each row and column in each m×n array being protected by the erasure-correcting code for the data. Each group of t storage devices contains extra second responder parities to correct extra data erasures in addition to data erasures corrected by first responder vertical parities in each m×t subarray, and w, n, m, l and t are positive integers.Type: ApplicationFiled: April 30, 2018Publication date: August 30, 2018Inventors: John S. Best, Mario Blaum, Steven R. Hetzler
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Patent number: 10055278Abstract: A computer-implemented method is provided for increasing the failure tolerance of an array of storage elements in a storage system. The computer-implemented method includes configuring an array to include a plurality of storage elements in n>1 sets of storage elements. The computer-implemented method also includes configuring an erasure-correcting code such that at least one column of the storage elements of the array stores row parity information, and at least one row of the storage elements of the array stores column parity information. Still yet, the computer-implemented method includes, subsequent to a failure of one of the storage elements storing data, selecting a recipient storage element from the array, and rebuilding at least a portion of the data onto the recipient storage element by performing a parity exchange operation that retains a failure tolerance of the set of storage elements containing the failed storage element.Type: GrantFiled: October 30, 2015Date of Patent: August 21, 2018Assignee: International Business Machines CorporationInventors: Mario Blaum, Steven R. Hetzler