Patents by Inventor Mario Casu

Mario Casu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6871330
    Abstract: A method for characterizing a CMOS logic cell of the partially depleted silicon-on-insulator type (PD-SOI) may include modeling the logic cell and determining internal potentials of transistors of the cell in a dynamic equilibrium state based upon a functional simulation of the modeled cell. This may be done using a binary stimulation signal having an initial logic value. The dynamic equilibrium state may be based upon a cancellation, to within a precision error, of the sum of the squares of variations in the quantities of charge in floating substrates of the transistors taken over a period of two successive transitions of the stimulation signal.
    Type: Grant
    Filed: May 29, 2003
    Date of Patent: March 22, 2005
    Assignee: STMicroelectronics SA
    Inventors: Philippe Flatresse, Mario Casu
  • Publication number: 20040054514
    Abstract: A method for characterizing a CMOS logic cell of the partially depleted silicon-on-insulator type (PD-SOI) may include modeling the logic cell and determining internal potentials of transistors of the cell in a dynamic equilibrium state based upon a functional simulation of the modeled cell. This may be done using a binary stimulation signal having an initial logic value. The dynamic equilibrium state may be based upon a cancellation, to within a precision error, of the sum of the squares of variations in the quantities of charge in floating substrates of the transistors taken over a period of two successive transitions of the stimulation signal.
    Type: Application
    Filed: May 29, 2003
    Publication date: March 18, 2004
    Applicant: STMicroelectronics SA
    Inventors: Philippe Flatresse, Mario Casu