Abstract: A multi-streaming processor has a plurality of streams for streaming one or more instruction threads, a set of functional resources for processing instructions from streams; and interstream control mechanisms whereby any stream may effect the operation of any other stream. In various embodiments the interstream control mechanisms include mechanisms for accomplishing one or more of enabling or disabling another stream, putting another stream into a sleep mode or awakening another stream from a sleep mode, setting priorities for another stream relative to access to functional resources, and granting blocking access by another stream to functional resources. A Master Mode is taught, wherein one stream is granted master status, and thereby may exert any and all available control mechanisms relative to other streams without interference by any stream.

Abstract: A multi-streaming processor has multiple streams for processing multiple threads, and an instruction scheduler including a priority record of priority codes for one or more of the streams. The priority codes determine in some embodiments relative access to resources as well as which stream has access at any point in time. In other embodiments priorities are determined dynamically and altered on-the-fly, which may be done by various criteria, such as on-chip processing statistics, by executing one or more priority algorithms, by input from off-chip, according to stream loading, or by combinations of these and other methods. In one embodiment a special code is used for disabling a stream, and streams may be enabled and disabled dynamically by various methods, such as by on-chip events, processing statistics, inpu from off-chip, and by processor interrupts. Some specific applications are taught, including for IP-routers and digital signal processors.

Abstract: A multi-streaming processor has a plurality of streams for streaming one or more instruction threads, a set of functional resources for processing instructions from streams; and interstream control mechanisms whereby any stream may effect the operation of any other stream. In various embodiments the interstream control mechanisms include mechanisms for accomplishing one or more of enabling or disabling another stream, putting another stream into a sleep mode or awakening another stream from a sleep mode, setting priorities for another stream relative to access to functional resources, and granting blocking access by another stream to functional resources. A Master Mode is taught, wherein one stream is granted master status, and thereby may exert any and all available control mechanisms relative to other streams without interference by any stream.

Abstract: A processing system has an instruction processor (IP), register files for storing data to be processed by the IP, such as a thread context, and a register transfer unit (RTU) connected to the register files and to the IP. Register files may assume different states, readable and settable by both the RTU and the IP. The IP and the RTU assume control of register files and perform their functions partially in response to states for the register files, and in releasing register files after processing, set the states. The invention is particularly applicable to multistreamed processors, wherein more register files than streams may be implemented, allowing for at least one idle register file in which to accomplish background loading and unloading of data. The invention is also particularly applicable to processing systems dealing with real-time phenomena, such as data packet processing in network routers.

Abstract: An integrated circuit (IC) includes multiple circuits and functions which share multiple internal signal buses, three physical and five logical, according to distributed bus access and control arbitration. The multiple internal signal buses are shared among three tiers of internal circuit functions: a central processing unit and a DMA controller; a DRAM controller and a bus interface unit; and peripheral interface circuits, such as PCMCIA and display controllers. Two of the physical buses correspond to two of the logical buses and are used for communications within the IC. The third physical bus corresponds to three of the logical buses and is used for communications between the IC and circuits external to the IC. Arbitration for accessing and controlling the various signal buses is distributed both within and among the three tiers of internal circuit functions.

Abstract: The invention is a method and apparatus for conditionally nullifying a current instruction based on a first test value where the first test value can be set in one or more prior instructions and where the execution of the current instruction can set a second test value without affecting the first test value. The one or more prior instructions which set the first test value need not immediately precede the current instruction. In a preferred embodiment, a test value comprises multiple bits, each bit capable of representing a unique state. A mask is provided to select the bits which are being tested. Also, means are provided for specifying an logical operation to be performed on the test values. The invention permits multiple status test results to be saved and concurrently tested in a single branch instruction.

Abstract: Memory requests are pipelined to an external memory by forming a memory address during the same clock cycle that the associated instruction is executed, issuing a ready signal during the clock cycle that precedes the clock cycle in which information is output from an external memory, and directing information received from the external memory to a register file during the same clock cycle that the information is received. In addition, when an instruction requires the information that was requested by the previous instruction, the information is directed to an arithmetic logic unit (ALU) during the same clock cycle that the information is received. As a result, the cycle time required to retrieve information stored in a DRAM can be substantially reduced.

Abstract: A computer with a pipelined processor and code breakpoints for performing software debug operations includes prefetch and decode stages, debug address registers for storing code breakpoints representing addresses of preselected instructions, and two digital comparators. During the instruction prefetch phase of operation, the first comparator compares the 29 most significant bits ?31:3! of the 32-bit prefetch instruction address against the code breakpoints stored in the debug address registers and produces a 1-bit signal indicating whether such comparison results in a positive match. Subsequently, during the decode phase of operation, the second comparator compares the three least significant bits ?2:0! of the 32-bit prefetch instruction address and produces a 1-bit signal indicating whether such comparison results in a positive match.

Abstract: A method and apparatus for implementing a new imaging and image composition system based on the real world metaphor of surface absorption, reflection, and transmission where many layers of translucent and opaque objects are composed into a final image for output to a video display. The algorithms are a substitution for both "Painter's algorithm" (the image composition technique traditionally used in computer graphic systems) and the alpha blending algorithms presently used in the computer and television industries for video special effects such as cross-fades between images, transparency, and color keying. In contrast to the prior art "colored pixel" algorithms, this system is based on a light propagation metaphor that uses virtual light source illumination and the absorption, reflection, and transmission properties of the objects in the image to create the final screen image. Thus, instead of representing each picture element (pixel) by color components specified by a chosen color model (e.g.

Abstract: The invention is an instruction for locating the address of a specific character or value within a byte string of variable length. An offset into a portion of the string is specified and the portion of the string is searched for a first occurrence of the specific character beginning at the specified offset. If the specific character is found, then the existence of the specific character is indicated and an address or offset of the specific character is saved or otherwise indicated. If the specific character is not found, then the non-existence of the specific character is indicated and a convenient address or offset for referencing the next character immediately following the portion of the string already examined is saved or otherwise indicated. The specific character can have a length of one or more bytes and can be a pre-defined fixed value or a dynamic arbitrary value. The invention can execute in a time period comparable to performing an arithmetic instruction.

Abstract: An associative memory is configurable to detect one of a plurality of relationships among a set of data, all within a number of cycles equal to the number of bits in the field of data upon which the sort is being executed. Because the memory is configurable, a single memory array can be used to accomplish a wide variety of results, either changing the relationship upon which the data is sorted on the fly, or providing a field programmable or mask programmable configuration input to adapt a given array design to a particular need. The array can be configured according to a configuration input to detect a relationship among fields of data stored in the memory selected from the group including "greater than", "greater than or equal to", "less than", "less than or equal to", "equal to", a minimum and a maximum. Further, the memory system can be adapted to detect the minimum of a first field in a given row and the maximum of a second field in a given row in parallel.

Abstract: A microprocessor is configured as two virtual processors having separate program counters, a common memory and a common execution unit. The processors are configured in a two stage pipeline arrangement and the instructions are interleaved so that as one processor fetches instructions the other executes. One processor runs a fixed length loop of single instructions to provide service of input/output pins at regular and frequent times to afford high resolution. The other processor runs multiple instruction routines. The instructions of either processor can modify the instructions of the other and determine whether a given instruction should be executed. The microprocesor is used as a coprocessor to relieve a main microprocessor of the burdens of managing I/O pins and of running some complex algorithms.

Abstract: A microprocessor is configured as two virtual processors having separate program counters, a common memory and a common execution unit. The processors are configured in a two stage pipeline arrangement and the instructions are interleaved so that as one processor fetches instructions the other executes. One processor runs a fixed length loop of single instructions to provide service of input/output pins at regular and frequency times to afford high resolution. The other processor runs multiple instruction routines. The instructions of either processor can modify the instructions of the other and determine whether a given instruction should be executed. The microprocessor is used as a coprocessor to relieve a main microprocessor of the burdens of managing I/O pins and of running some complex algorithms.

Abstract: A vehicle anti-theft device is disclosed which includes an electronically erasable programmable read only memory (EEPROM) which stores a modifiable code which must be matched by an input code in order to start the vehicle. The ignition key includes a resistor pellet, engaged by contact in the ignition lock assembly, which is measured to provide the input code. To avoid problems associated with intermittent contact engagement with the resistor pellet, circuitry is provided to control the resistor measurement cycle.