Patents by Inventor Mario De Matteis

Mario De Matteis has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method for accessing a multilevel nonvolatile memory device of the flash NAND type
    Patent number: 7382660
    Abstract: Multi-level programming allows for writing a first and a second bit in selected cells by separately programming the first bit from the second bit. Programming of the first bit determines a shifting from a first threshold level to a second threshold level. Programming of the second bit requires a preliminary reading to detect whether the first bit has been modified, performing a first writing step to bring the cell to a third threshold voltage if the first bit has been modified and performing a second writing step to bring the selected cell to a fourth threshold voltage different from the third threshold level if the first bit has not been modified. For increasing reading and program reliability, during preliminary reading of the second portion a reading result is forced to correspond to the first threshold level.
    Type: Grant
    Filed: July 20, 2006
    Date of Patent: June 3, 2008
    Assignees: STMicroelectronics S.R.L., Hynix Semiconductor Inc.
    Inventors: Angelo Bovino, Vincenzo Altieri, Roberto Ravasio, Rino Micheloni, Mario De Matteis
  • METHOD FOR ACCESSING A MULTILEVEL NONVOLATILE MEMORY DEVICE OF THE FLASH NAND TYPE
    Publication number: 20070047299
    Abstract: Multi-level programming allows for writing a first and a second bit in selected cells by separately programming the first bit from the second bit. Programming of the first bit determines a shifting from a first threshold level to a second threshold level. Programming of the second bit requires a preliminary reading to detect whether the first bit has been modified, performing a first writing step to bring the cell to a third threshold voltage if the first bit has been modified and performing a second writing step to bring the selected cell to a fourth threshold voltage different from the third threshold level if the first bit has not been modified. For increasing reading and program reliability, during preliminary reading of the second portion a reading result is forced to correspond to the first threshold level.
    Type: Application
    Filed: July 20, 2006
    Publication date: March 1, 2007
    Applicants: STMicroelectronics S.r.l., Hynix Semiconductor Inc.
    Inventors: Angelo Bovino, Vincenzo Altieri, Roberto Ravasio, Rino Micheloni, Mario De Matteis