Abstract: A C-MOS sense amplifier capable of detecting voltage differences between the signals applied to its inputs in correspondence with the clock signal transitions. The amplifier has a level converter, a sense circuit and a feedback block which are inactive in a first inactive phase of the clock signal, while in a second active phase, immediately after clock signal transition, the sense amplifier attains the operating point necessary to activate the level converter and the sense circuit. Hence a high positive feedback is started which switches the sense circuit. Finally, after the level transition of a delayed clock signal, the feedback signal generated by the feedback block reduces to zero the dissipation of the whole differential sense amplifier.

Abstract: The basic element provided by the invention carries out the basic logic functions of storage and/or transfer of the data applied at the input, typical of a latch. Two ways of embodiment of the basic element having active phase at the high and low level of the clock signal are described. The basic element presents a transfer-gate transistor at the input controlled by the clock signal, followed by an inverter at whose signal leads two positive feedback networks are connected, one of which controlled by the clock signal, to stabilize the logic levels (FIG. 1).