Patents by Inventor Mario Flajslik

Mario Flajslik has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11477122
    Abstract: Technologies for improving throughput in a network include a node switch. The node switch is to obtain expected performance data indicative of an expected data transfer performance of the node switch. The node switch is also to obtain measured performance data indicative of a measured data transfer performance of the node switch, compare the measured performance data to the expected performance data to determine whether the measured data transfer performance satisfies the expected data transfer performance, determine, as a function of whether the measured data transfer performance satisfies the expected data transfer performance, whether to force a unit of data through a non-minimal path to a destination, and send, in response to a determination to force the unit of data to be sent through a non-minimal path, the unit of data to an output port of the node switch associated with the non-minimal path. Other embodiments are also described.
    Type: Grant
    Filed: September 27, 2017
    Date of Patent: October 18, 2022
    Assignee: Intel Corporation
    Inventors: Mario Flajslik, Eric R. Borch, Timo Schneider, Michael A. Parker
  • Publication number: 20220029839
    Abstract: Technologies for densely packaging network components for large scale indirect topologies include group of switches. The group of switches includes a stack of node switches that includes a first set of ports and a stack of global switches that includes a second set of ports. The stack of node switches are oriented orthogonally to the stack of global switches. Additionally, the first set of ports are oriented towards the second set of ports and the node switches are connected to the global switches through the first and second sets of ports. Other embodiments are also described and claimed.
    Type: Application
    Filed: October 5, 2021
    Publication date: January 27, 2022
    Inventors: Mario Flajslik, Eric R. Borch, Michael A. Parker, Richard J. Dischler
  • Patent number: 11194636
    Abstract: Technologies for generating triggered conditional events operations include a host fabric interface (HFI) of a compute device configured to receive an operation execution command message associated with a triggered operation that has been fired, process the received operation execution command message to extract and store argument information from the received operation execution command, and increment an event counter associated with the fired triggered operation. The HFI is further configured to perform a triggered compare-and-generate event (TCAGE) operation as a function of the extracted argument information, determine whether to generate a triggering event, generate the triggering event as a function of the performed TCAGE operation, insert the generated triggered event into a triggered operation queue, and update the value of the event counter. Other embodiments are described herein.
    Type: Grant
    Filed: March 30, 2018
    Date of Patent: December 7, 2021
    Assignee: Intel Corporation
    Inventors: Mario Flajslik, Keith D. Underwood, Timo Schneider, James Dinan
  • Patent number: 11188394
    Abstract: Technologies for synchronizing triggered operations include a host fabric interface (HFI) of a compute device configured to receive an operation execution command associated with a triggered operation that has been fired and determine whether the operation execution command includes an instruction to update a table entry of a table managed by the HFI. Additionally, the HFI is configured to issue, in response to a determination that the operation execution command includes the instruction to update the table entry, a triggered list enable (TLE) operation and a triggered list disable (TLD) operation to a table manager of the HFI and disable a corresponding table entry in response to the TLD operation having been triggered, the identified table entry. The HFI is further configured to execute one or more command operations associated with the received operation execution command and re-enable, in response to the TLE operation having been triggered, the table entry. Other embodiments are described herein.
    Type: Grant
    Filed: March 30, 2018
    Date of Patent: November 30, 2021
    Assignee: Intel Corporation
    Inventors: James Dinan, Mario Flajslik, Timo Schneider, Keith D. Underwood
  • Patent number: 11157336
    Abstract: Technologies for extending triggered operations include a host fabric interface (HFI) of a compute device configured to detect a triggering event associated with a counter, increment the counter, and determine whether a value of the counter matches a trigger threshold of a triggered operation in a triggered operation queue associated with the counter. The HFI is further configured to execute, one or more commands associated with the triggered operation upon determining that the value of the counter matches the trigger threshold, and determine, subsequent to the execution of the one or more commands, whether the triggered operation corresponds to a recurring triggered operation. The HFI is additionally configured to increment, in response to a determination that the triggered operation corresponds to a recurring triggered operation, the value of the trigger threshold by a threshold increment and re-insert the triggered operation into the triggered operation queue. Other embodiments are described herein.
    Type: Grant
    Filed: December 30, 2017
    Date of Patent: October 26, 2021
    Assignee: Intel Corporation
    Inventors: James Dinan, Mario Flajslik, Timo Schneider, Keith D. Underwood
  • Patent number: 11153105
    Abstract: Technologies for densely packaging network components for large scale indirect topologies include group of switches. The group of switches includes a stack of node switches that includes a first set of ports and a stack of global switches that includes a second set of ports. The stack of node switches are oriented orthogonally to the stack of global switches. Additionally, the first set of ports are oriented towards the second set of ports and the node switches are connected to the global switches through the first and second sets of ports. Other embodiments are also described and claimed.
    Type: Grant
    Filed: June 29, 2017
    Date of Patent: October 19, 2021
    Assignee: Intel Corporation
    Inventors: Mario Flajslik, Eric R. Borch, Michael A. Parker, Richard J. Dischler
  • Publication number: 20210255910
    Abstract: Systems, apparatuses and methods may provide for detecting an outbound communication and identifying a context of the outbound communication. Additionally, a completion status of the outbound communication may be tracked relative to the context. In one example, tracking the completion status includes incrementing a sent messages counter associated with the context in response to the outbound communication, detecting an acknowledgement of the outbound communication based on a network response to the outbound communication, incrementing a received acknowledgements counter associated with the context in response to the acknowledgement, comparing the sent messages counter to the received acknowledgements counter, and triggering a per-context memory ordering operation if the sent messages counter and the received acknowledgements counter have matching values.
    Type: Application
    Filed: May 21, 2020
    Publication date: August 19, 2021
    Applicant: Intel Corporation
    Inventors: Mario Flajslik, James Dinan
  • Patent number: 11023275
    Abstract: Technologies for managing a queue on a compute device are disclosed. In the illustrative embodiment, the queue is managed by a host fabric interface of the compute device. Queue operations such as enqueuing data onto the queue and dequeuing data from the queue may be requested by remote compute devices by sending queue operations which may be processed by the host fabric interface. The host fabric interface may, in some embodiments, fully manage the queue without any assistance from the processor of the compute device. In other embodiments, the processor of the compute device may be responsible for certain tasks, such as garbage collection.
    Type: Grant
    Filed: February 9, 2017
    Date of Patent: June 1, 2021
    Assignee: Intel Corporation
    Inventors: James Dinan, Mario Flajslik, Timo Schneider
  • Patent number: 10963183
    Abstract: Technologies for fine-grained completion tracking of memory buffer accesses include a compute device. The compute device is to establish multiple counter pairs for a memory buffer. Each counter pair includes a locally managed offset and a completion counter. The compute device is also to receive a request from a remote compute device to access the memory buffer, assign one of the counter pairs to the request, advance the locally managed offset of the assigned counter pair by the amount of data to be read or written, and advance the completion counter of the assigned counter pair as the data is read from or written to the memory buffer. Other embodiments are also described and claimed.
    Type: Grant
    Filed: March 20, 2017
    Date of Patent: March 30, 2021
    Assignee: Intel Corporation
    Inventors: James Dinan, Keith D. Underwood, Sayantan Sur, Charles A. Giefer, Mario Flajslik
  • Patent number: 10958589
    Abstract: Technologies for offloaded management of communication are disclosed. In order to manage communication with information that may be available to applications in a compute device, the compute device may offload communication management to a host fabric interface using a credit management system. A credit limit is established, and each message to be sent is added to a queue with a corresponding number of credits required to send the message. The host fabric interface of the compute device may send out messages as credits become available and decrease the number of available credits based on the number of credits required to send a particular message. When an acknowledgement of receipt of a message is received, the number of credits required to send the corresponding message may be added back to an available credit pool.
    Type: Grant
    Filed: March 29, 2017
    Date of Patent: March 23, 2021
    Assignee: Intel Corporation
    Inventors: James Dinan, Sayantan Sur, Mario Flajslik, Keith D. Underwood
  • Patent number: 10693787
    Abstract: Techniques are disclosed to throttle bandwidth imbalanced data transfers. In some examples, an example computer-implemented method may include splitting a payload of a data transfer operation over a network fabric into multiple chunk get operations, starting the execution of a threshold number of the chunk get operations, and scheduling the remaining chunk get operations for subsequent execution. The method may also include executing a scheduled chunk get operation in response determining a completion of an executing chunk get operation. In some embodiments, the chunk get operations may be implemented as triggered operations.
    Type: Grant
    Filed: August 25, 2017
    Date of Patent: June 23, 2020
    Assignee: Intel Corporation
    Inventors: Timo Schneider, Keith D. Underwood, Mario Flajslik, Sayantan Sur, James Dinan
  • Patent number: 10671457
    Abstract: Systems, apparatuses and methods may provide for detecting an outbound communication and identifying a context of the outbound communication. Additionally, a completion status of the outbound communication may be tracked relative to the context. In one example, tracking the completion status includes incrementing a sent messages counter associated with the context in response to the outbound communication, detecting an acknowledgement of the outbound communication based on a network response to the outbound communication, incrementing a received acknowledgements counter associated with the context in response to the acknowledgement, comparing the sent messages counter to the received acknowledgements counter, and triggering a per-context memory ordering operation if the sent messages counter and the received acknowledgements counter have matching values.
    Type: Grant
    Filed: March 27, 2015
    Date of Patent: June 2, 2020
    Assignee: Intel Corporation
    Inventors: Mario Flajslik, James Dinan
  • Patent number: 10574733
    Abstract: Technologies for handling message passing interface receive operations include a compute node to determine a plurality of parameters of a receive entry to be posted and determine whether the plurality of parameters includes a wildcard entry. The compute node generates a hash based on at least one parameter of the plurality of parameters in response to determining that the plurality of parameters does not include the wildcard entry and appends the receive entry to a list in a bin of a posted receive data structure, wherein the bin is determined based on the generated hash. The compute node further tracks the wildcard entry in the posted receive data structure in response to determining the plurality of parameters includes the wildcard entry and appends the receive entry to a wildcard list of the posted receive data structure in response to tracking the wildcard entry.
    Type: Grant
    Filed: September 18, 2015
    Date of Patent: February 25, 2020
    Assignee: Intel Corporation
    Inventors: James Dinan, Mario Flajslik, Keith D. Underwood
  • Patent number: 10554568
    Abstract: Technologies for estimating network round-trip times include a sender computing node in network communication with a set of neighboring computing nodes. The sender computing node is configured to determine the set of neighboring computing nodes, as well as a plurality of subsets of the set of neighboring computing nodes. Accordingly, the sender computing node generates a message queue for each of the plurality of subsets, each message queue including a probe message for each neighboring node in the subset to which the message queue corresponds. The sender computing node is further configured to determine a round-trip time for each message queue (i.e., subset of neighboring computing nodes) based on a duration of time between the first probe message of the message queue being transmitted and an acknowledgment being received in response to the last probe message of the message queue being transmitted.
    Type: Grant
    Filed: September 25, 2015
    Date of Patent: February 4, 2020
    Assignee: Intel Corporation
    Inventors: Mario Flajslik, James Dinan
  • Patent number: 10439946
    Abstract: Technologies for endpoint congestion avoidance are disclosed. In order to avoid congestion caused by a network fabric that can transport data to a compute device faster than the compute device can store the data in a particular type of memory, the compute device may in the illustrative embodiment determine a suitable data transfer rate and communicate an indication of the data transfer rate to the remote compute device which is sending the data. The remote compute device may then send the data at the indicated data transfer rate, thus avoiding congestion.
    Type: Grant
    Filed: February 10, 2017
    Date of Patent: October 8, 2019
    Assignee: INTEL CORPORATION
    Inventors: James Dinan, Mario Flajslik, Robert C. Zak
  • Patent number: 10394738
    Abstract: Technologies for a system of communicatively coupled network switches in a hierarchical interconnect network topology include two or more groups that each include two or more first and second level switches in which each of the first level switches are communicatively coupled to each of the plurality of second level switches to form a complete bipartite graph. Additionally, each of the groups is interconnected to each of the other groups via a corresponding global link connecting a second level switch of one group to a corresponding second level switch of another group. Further, each of the first level switches are communicatively coupled to one or more computing nodes. Other embodiments are described herein.
    Type: Grant
    Filed: September 29, 2016
    Date of Patent: August 27, 2019
    Assignee: Intel Corporation
    Inventors: Mario Flajslik, Eric R. Borch, Michael A. Parker, Wayne A. Downer
  • Patent number: 10389636
    Abstract: Technologies for adaptive routing based on network traffic pattern characterization include a network switch configured to receive a network packet via one of a plurality of input ports and identify a set of the plurality of output ports associated with a path usable to forward the received network packet to a destination computing device along. The network switch is further configured to adjust a total congestion value for each of the set of output ports based on a type of the path to which each of the set of output ports corresponds and a value of a minimal path counter to which each of the set of output ports corresponds and enqueue the received network packet into an output buffer queue of one of the set of output ports based on the total congestion value. Other embodiments are described herein.
    Type: Grant
    Filed: July 1, 2016
    Date of Patent: August 20, 2019
    Assignee: Intel Corporation
    Inventors: Mario Flajslik, Eric R. Borch, Michael A. Parker
  • Patent number: 10333848
    Abstract: Technologies for adaptive routing using throughput estimation that includes a network switch. The network switch is configured to determine an adjusted average saturation count for each output buffer queue as a function of a present value of a saturation counter of a corresponding output buffer queue and a weighted average saturation count and a running average saturation count for each of the plurality of output buffer queues as a function of the corresponding captured present value and the adjusted average saturation count. The network switch is further configured to determine a congestion rate value for each output buffer queue and a total congestion value as a function of the congestion rate values and a standard occupancy congestion corresponding to a respective one of the plurality of output buffer queues. Other embodiments are described herein.
    Type: Grant
    Filed: July 1, 2016
    Date of Patent: June 25, 2019
    Assignee: Intel Corporation
    Inventors: Mario Flajslik, Eric R. Borch, Michael A. Parker, Scott S. Diesing
  • Patent number: 10305805
    Abstract: Technologies for adaptive routing based on aggregated congestion information include a network switch that includes a plurality of output ports. The network switch is configured to determine a maximum local occupancy count for each output port based on a maximum local occupancy count of output buffer queues of each output port, a local congestion value based on the maximum local occupancy count, and a remote congestion value for a corresponding remote input buffer queue of a remote computing device communicatively coupled to a corresponding output port. The network switch is further configured to determine, for each output port, a total congestion value as a function of the local congestion value and the remote congestion value and enqueue the network packet into one of the output buffer queues of one of the output ports based on the total congestion values of the output ports. Other embodiments are described herein.
    Type: Grant
    Filed: July 1, 2016
    Date of Patent: May 28, 2019
    Assignee: Intel Corporation
    Inventors: Mario Flajslik, Eric R. Borch, Michael A. Parker
  • Patent number: 10250524
    Abstract: Technologies for increasing the bandwidth of partitioned hierarchical networks is disclosed. If each partition of network groups of a computer network are isolated, then the connections between the network groups of different partitions may go unused. However, careful selection of the network connections between partitions of different network groups may allow for a pseudo-direct connection between two network groups of the same partition using a single non-blocking switch in a network group of a different partition. Such a configuration can increase the effective bandwidth available within a partition without affecting the bandwidth available in another partition.
    Type: Grant
    Filed: September 23, 2016
    Date of Patent: April 2, 2019
    Assignee: Intel Corporation
    Inventors: Mario Flajslik, Gene Wu, Michael A. Parker