Patents by Inventor Mario G. Ancona

Mario G. Ancona has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9006708
    Abstract: A semiconductor device including a heterostructure having at least one low-resistivity p-type GaSb quantum well is provided. The heterostructure includes a layer of In0.52Al0.48As on an InP substrate, where the In0.52Al0.48As is lattice matched to InP, followed by an AlAsxSb1-x buffer layer on the In0.52Al0.48As layer, an AlAsxSb1-x spacer layer on the AlAsxSb1-x buffer layer, a GaSb quantum well layer on the AlAsxSb1-x spacer layer, an AlAsxSb1-x barrier layer on the GaSb quantum well layer, an In0.2Al0.8Sb etch-stop layer on the AlAsxSb1-x barrier layer, and an InAs cap. The semiconductor device is suitable for use in low-power electronic devices such as field-effect transistors.
    Type: Grant
    Filed: May 16, 2013
    Date of Patent: April 14, 2015
    Assignee: The United States of America, as represented by the Secretary of the Navy
    Inventors: Brian R. Bennett, Theresa F. Chick, Mario G. Ancona, John Bradley Boos
  • Publication number: 20140339501
    Abstract: A semiconductor device including a heterostructure having at least one low-resistivity p-type GaSb quantum well is provided. The heterostructure includes a layer of InwAl1?wAs on a semi-insulating (100) InP substrate, where the InwAl1?wAs is lattice matched to InP, followed by an AlAsxSb1?x buffer layer on the InwAl1?wAs layer, an AlAsxSb1?x spacer layer on the buffer layer, a GaSb quantum well layer on the spacer layer, an AlAsxSb1?x barrier layer on the quantum well layer, an InyAl1?ySb layer on the barrier layer, and an InAs cap. The semiconductor device is suitable for use in low-power electronic devices such as field-effect transistors.
    Type: Application
    Filed: May 16, 2013
    Publication date: November 20, 2014
    Applicant: The Government of the United States of America, as represented by the Secretary of the Navy
    Inventors: Brian R. Bennett, Theresa F. Chick, Mario G. Ancona, John Bradley Boos
  • Publication number: 20140217363
    Abstract: A semiconductor device including a heterostructure having at least one low-resistivity p-type GaSb quantum well is provided. The heterostructure includes a layer of In0.52Al0.48As on an InP substrate, where the In0.52Al0.48As is lattice matched to InP, followed by an AlAsxSb1-x buffer layer on the In0.52Al0.48As layer, an AlAsxSb1-x spacer layer on the AlAsxSb1-x buffer layer, a GaSb quantum well layer on the AlAsxSb1-x spacer layer, an AlAsxSb1-x barrier layer on the GaSb quantum well layer, an In0.2Al0.8Sb etch-stop layer on the AlAsxSb1-x barrier layer, and an InAs cap. The semiconductor device is suitable for use in low-power electronic devices such as field-effect transistors.
    Type: Application
    Filed: May 16, 2013
    Publication date: August 7, 2014
    Applicant: The Government of the United States of America, as represented by the Secretary of the Navy
    Inventors: Brian R. Bennett, Theresa F. Chick, Mario G. Ancona, John Bradley Boos
  • Patent number: 5838021
    Abstract: Disclosed are single electron digital devices, in which the screening lengths of individual device islands are between 0.5 and 1.0 islands. This range permits island occupancy to be bias independent, permitting the devices to hold or process digital information independent of device biases. This range of screening lengths can be effected by choice of device parameters which are sufficiently modest to permit practical fabrication of these devices.
    Type: Grant
    Filed: December 26, 1996
    Date of Patent: November 17, 1998
    Inventor: Mario G. Ancona