Patents by Inventor Mario G. Saggio

Mario G. Saggio has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • POWER ELECTRONIC DEVICE OF MULTI-DRAIN TYPE INTEGRATED ON A SEMICONDUCTOR SUBSTRATE AND RELATIVE MANUFACTURING PROCESS
    Publication number: 20090176341
    Abstract: A power electronic device is integrated on a semiconductor substrate of a first type of conductivity. The device includes a plurality of elemental units, and each elemental unit includes a body region of a second type of conductivity which is realized on a semiconductor layer of the first type of conductivity formed on the semiconductor substrate, and a column region of the first type of conductivity which is realized in said semiconductor layer below the body region. The semiconductor layer includes multiple semiconductor layers which overlap each other. The resistivity of each layer is different from that of the other layers. The column region includes a plurality of doped sub-regions, each realized in one of the semiconductor layers. The amount of charge of each doped sub-region balances the amount of charge of the corresponding semiconductor layer in which each doped sub-region is realized.
    Type: Application
    Filed: January 8, 2009
    Publication date: July 9, 2009
    Applicant: STMicroelectronics S.r.I.
    Inventors: Mario G. Saggio, Ferruccio Frisina
  • Power electronic device of multi-drain type integrated on a semiconductor substrate and relative manufacturing process
    Patent number: 7498619
    Abstract: A power electronic device is integrated on a semiconductor substrate of a first type of conductivity. The device includes a plurality of elemental units, and each elemental unit includes a body region of a second type of conductivity which is realized on a semiconductor layer of the first type of conductivity formed on the semiconductor substrate, and a column region of the first type of conductivity which is realized in said semiconductor layer below the body region. The semiconductor layer includes multiple semiconductor layers which overlap each other. The resistivity of each layer is different from that of the other layers. The column region includes a plurality of doped sub-regions, each realized in one of the semiconductor layers. The amount of charge of each doped sub-region balances the amount of charge of the corresponding semiconductor layer in which each doped sub-region is realized.
    Type: Grant
    Filed: February 23, 2006
    Date of Patent: March 3, 2009
    Assignee: STMicroelectronics S.r.l.
    Inventors: Mario G. Saggio, Ferruccio Frisina