Patents by Inventor Mario Ghezzo

Mario Ghezzo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6127812
    Abstract: In embodiments of the present invention, an energy extractor includes a capacitor which experiences capacitance and voltage changes in response to movement of a capacitor plate or of a dielectric material. In one embodiment, a third plate is positioned between first and second plates to create two capacitors of varying capacitances. In another embodiment, one capacitor plate is attached by flexible arms which permit movement across another capacitor plate. The above capacitors can be used singularly or with one or more other capacitors and are rectified either individually or in a cascaded arrangement for supplying power to a rechargeable energy source. The above capacitors can be fabricated on a substrate along with supporting electronics such as diodes.
    Type: Grant
    Filed: February 16, 1999
    Date of Patent: October 3, 2000
    Assignee: General Electric Company
    Inventors: Mario Ghezzo, Paul Andrew Frank, John Erik Hershey
  • Patent number: 6067931
    Abstract: A thermal processor for at least one semiconductor wafer includes a reactor chamber having a material substantially transparent to light including a wavelength within the range of about 200 nanometers to about 800 nanometers for holding the at least one semiconductor wafer. A coating including a material substantially reflective of infrared radiation can be present on at least a portion of the reactor chamber. A light source provides radiant energy to the at least one semiconductor wafer through the coating and the reactor chamber. The light source can include an ultraviolet discharge lamp, a halogen infrared incandescent lamp, or a metal halide visible discharge lamp. The coating can be situated on an inner or outer surface of the reactor chamber. If the reactor chamber has inner and outer walls, the coating can be situated on either the inner wall or the outer wall.
    Type: Grant
    Filed: November 4, 1996
    Date of Patent: May 30, 2000
    Assignee: General Electric Company
    Inventors: Mario Ghezzo, Timothy Dietrich Page, Thomas Bert Gorczyca, Rolf Sverre Bergman, Himanshu Bachubhai Vakil, Charles Samuel Huey, Seth David Silverstein
  • Patent number: 5814859
    Abstract: A semiconductor device includes a semiconductor substrate having an epitaxial layer surface opposite a drain contact surface; a semiconductor layer adjacent to the epitaxial layer surface of the substrate, the semiconductor layer including material of a first conductivity type; a patterned refractory dielectric layer adjacent to the semiconductor layer; a base region of implanted ions in the semiconductor layer, the base region being of a second conductivity type; a source region of implanted ions in the base region, the source region being of the first conductivity type; a gate insulator layer adjacent to at least a portion of the source and base regions of the semiconductor layer; and a gate electrode over a portion of the gate insulator layer, adjacent to and in physical contact with an outer edge of the patterned refractory dielectric layer, and over at least a portion of the base region between the source region and the patterned refractory dielectric layer.
    Type: Grant
    Filed: November 15, 1995
    Date of Patent: September 29, 1998
    Assignee: General Electric Company
    Inventors: Mario Ghezzo, Tat-Sing Paul Chow, James William Kretchmer, Richard Joseph Saia, William Andrew Hennessy
  • Patent number: 5776275
    Abstract: A magnetic circulator is incorporated into a multi-chip module using a microwave high density interconnect (HDI) structure. A prepackaged circulator can be inserted into a ready-made high density interconnected multi-chip module; this prepackaged circulator may use a stripline design having a signal line with two ground planes above and below the signal line, or a microstrip transmission line design having one signal line and one ground plane below the signal line. Alternatively a circulator can be manufactured directly in a high density interconnected multi-chip module, with a stripline, or a microstrip transmission line design.
    Type: Grant
    Filed: October 21, 1996
    Date of Patent: July 7, 1998
    Assignee: Martin Marietta Corporation
    Inventors: Vikram Bidare Krishnamurthy, Kyung Wook Paik, Mario Ghezzo, William Paul Kornrumpf, Eric Joseph Wildi
  • Patent number: 5653841
    Abstract: A magnetic circulator is incorporated into a multi-chip module using a microwave high density interconnect (HDI) structure. A prepackaged circulator can be inserted into a ready-made high density interconnected multi-chip module; this prepackaged circulator may use a stripline design having a signal line with two ground planes above and below the signal line, or a microstrip transmission line design having one signal line and one ground plane below the signal line. Alternatively a circulator can be manufactured directly in a high density interconnected multi-chip module, with a stripline, or a microstrip transmission line design.
    Type: Grant
    Filed: April 13, 1995
    Date of Patent: August 5, 1997
    Assignee: Martin Marietta Corporation
    Inventors: Vikram Bidare Krishnamurthy, Kyung Wook Paik, Mario Ghezzo, William Paul Kornrumpf, Eric Joseph Wildi
  • Patent number: 5652559
    Abstract: An insulating layer with at least one via is provided over a metal plate. A sacrificial layer is applied over a portion of the insulating layer so that the sacrificial layer extends into the via. A metal bridge having at least one opening is provided over a portion of the sacrificial layer and a portion of the insulating layer so that the metal bridge extends over the via and the opening is situated adjacent a portion of the sacrificial layer. A reinforcing seal layer with a well is provided over the metal bridge so that the well is situated adjacent to at least a portion of the opening. The sacrificial layer is then removed.
    Type: Grant
    Filed: April 1, 1996
    Date of Patent: July 29, 1997
    Assignee: General Electric Company
    Inventors: Richard Joseph Saia, Mario Ghezzo, Bharat Sampath Kumar Bagepalli, Kevin Matthew Durocher
  • Patent number: 5531018
    Abstract: An insulating layer with at least one via is provided over a metal plate. A sacrificial layer is applied over a portion of the insulating layer so that the sacrificial layer extends into the via. A metal bridge having at least one opening is provided over a portion of the sacrificial layer and a portion of the insulating layer so that the metal bridge extends over the via and the opening is situated adjacent a portion of the sacrificial layer. A reinforcing seal layer with a well is provided over the metal bridge so that the well is situated adjacent to at least a portion of the opening. The sacrificial layer is then removed.
    Type: Grant
    Filed: December 20, 1993
    Date of Patent: July 2, 1996
    Assignee: General Electric Company
    Inventors: Richard J. Saia, Mario Ghezzo, Bharat S. K. Bagepalli, Kevin M. Durocher
  • Patent number: 5510281
    Abstract: A method for fabricating a semiconductor device includes patterning a refractory dielectric layer over a semiconductor layer of a first conductivity type; conformally depositing a first spacer layer over the patterned refractory dielectric layer and the semiconductor layer; patterning the first spacer layer to leave a first spacer adjacent to an edge of the patterned refractory dielectric layer; implanting ions of a second conductivity type to form a base region in the semiconductor layer; conformally depositing a second spacer layer over the patterned refractory dielectric layer and the semiconductor layer; patterning the second spacer layer to leave a second spacer adjacent to an edge of the first spacer; implanting ions of the first conductivity type to form a source region in the base region; removing the first and second spacers; applying a gate insulator layer over at least a portion of the semiconductor layer; conformally depositing a gate electrode layer over the gate insulator layer and the semicondu
    Type: Grant
    Filed: March 20, 1995
    Date of Patent: April 23, 1996
    Assignee: General Electric Company
    Inventors: Mario Ghezzo, Tat-Sing P. Chow, James W. Kretchmer, Richard J. Saia, William A. Hennessy
  • Patent number: 5510632
    Abstract: A silicon carbide (SiC) junction field effect transistor (JFET) device is fabricated upon a substrate layer, such as a p type conductivity SiC substrate, using ion implantation for the source and drain areas. A SiC p type conductivity layer is epitaxially grown on the substrate. A SiC n type conductivity layer is formed by ion implantation or epitaxial deposition upon the p type layer. The contacting surfaces of the p and n type layers form a junction. A p+ type gate area supported by the n type layer is formed either by the process of ion implantation or the process of depositing and patterning a second p type layer. The source and drain areas are heavily doped to n+ type conductivity by implanting donor ions in the n type layer.
    Type: Grant
    Filed: May 11, 1995
    Date of Patent: April 23, 1996
    Assignee: General Electric Company
    Inventors: Dale M. Brown, Mario Ghezzo
  • Patent number: 5475353
    Abstract: A micromachined electromagnetic switch, including two soft magnets situated in fixed positions above and below a permanent magnet, toggles between two fixed positions by the application of current in an actuator coil for a brief period. The permanent magnet is attached to a micromachined hinge or spring which moves under the action of a net force, thereby opening or closing the switch. Current in the actuator coil changes the relative strength of the magnetic forces due to the soft magnets. In the absence of current in the actuator coil, the switch is kept in the open or closed position by the attractive magnetic force between the permanent magnet and either the upper or lower soft magnet, whereby the stronger force is exercised between the permanent magnet and the nearest soft magnet.
    Type: Grant
    Filed: September 30, 1994
    Date of Patent: December 12, 1995
    Assignee: General Electric Company
    Inventors: Waseem A. Roshen, Mario Ghezzo, Richard J. Saia, William A. Hennessy, Bharat S. Bagepalli
  • Patent number: 5472539
    Abstract: A low temperature batch method for forming and positioning permanent magnets on electromagnetically actuated micro-fabricated components, such as electrical switches employs a first adhesive, such as a Siltem/epoxy blend of an epoxy resin and a siloxane polyimide polymer, to releasably attach a mold layer of Kapton polyimide to a substrate, which may be the movable portion of a micromechanical structure, or a precursor to such movable portion. A well-shape cavity is formed in the mold layer, and filled with a slurry of rare earth NdFeB magnetic particles suspended in a second adhesive, which is cured to form the body of a magnet. The second adhesive is an SPI/epoxy blend, also of an epoxy resin and a siloxane polyimide polymer, but with a greater adhesion strength and a higher temperature softening point compared to the Siltem/epoxy blend. The entire structure is heated, and the mold layer is pulled off the substrate, while the body of magnetic material remains firmly attached.
    Type: Grant
    Filed: June 6, 1994
    Date of Patent: December 5, 1995
    Assignee: General Electric Company
    Inventors: Richard J. Saia, Kevin M. Durocher, Thomas B. Gorczyca, Mario Ghezzo
  • Patent number: 5454904
    Abstract: Micromachining methods for fabricating micromechanical structures which include plunger elements free to reciprocate within cavities are fabricated using processing steps in common with those employed in high density interconnect (HDI) technology for multi-chip module packaging. A polymer, such as a polyimide, is utilized as a micromachinable material. In one embodiment, cavities are formed in the polymer material by laser ablation, employing a sacrificial layer as a mask. Electroplated copper may be employed as a sacrificial release layer. One particular structure is a micromechanical electric switch including an array of individual switch contacts actuatable in common.
    Type: Grant
    Filed: August 5, 1994
    Date of Patent: October 3, 1995
    Assignee: General Electric Company
    Inventors: Mario Ghezzo, Richard J. Saia, Bharat S. Bagepalli, Imdad Imam, Dennis L. Polla
  • Patent number: 5430597
    Abstract: A circuit interruption device having a plurality of micromechanical switches mounted on a substrate in a parallel-series array. The array includes a plurality of line branches connected in parallel in a circuit line. Each of the line branches has at least two of the switches serially connected therein. The micromechanical switches each has a pair of contacts formed on the substrate, a bridging contact movably formed on the substrate, and an actuator for causing the bridging contact to move in and out of contact with the contacts. The bridging contact can be either a member slidably disposed in a channel formed on the substrate or member attached to an end of a cantilever having its other end attached to the substrate. The actuator is controlled by a trip device which is also mounted on the substrate. The trip device senses the current in the circuit line and causes the switches to open when a predetermined level of current in the line is exceeded.
    Type: Grant
    Filed: January 4, 1993
    Date of Patent: July 4, 1995
    Assignee: General Electric Company
    Inventors: Bharat S. Bagepalli, Mario Ghezzo, Richard J. Saia, Imdad Imam
  • Patent number: 5378642
    Abstract: A silicon carbide (SiC) junction field effect transistor (JFET) device is fabricated upon a substrate layer, such as a p type conductivity SiC substrate, using ion implantation for the source and drain areas. A SiC p type conductivity layer is epitaxially grown on the substrate. A SiC n type conductivity layer is formed by ion implantation or epitaxial deposition upon the p type layer. The contacting surfaces of the p and n type layers form a junction. A p+ type gate area supported by the n type layer is formed either by the process of ion implantation or the process of depositing and patterning a second p type layer. The source and drain areas are heavily doped to n+ type conductivity by implanting donor ions in the n type layer.
    Type: Grant
    Filed: April 19, 1993
    Date of Patent: January 3, 1995
    Assignee: General Electric Company
    Inventors: Dale M. Brown, Mario Ghezzo
  • Patent number: 5374792
    Abstract: Micromachining methods for fabricating micromechanical structures which include plunger elements free to reciprocate within cavities are fabricated using processing steps in common with those employed in high density interconnect (HDI) technology for multi-chip module packaging. A polymer, such as a polyimide, is utilized as a micromachinable material. In one embodiment, cavities are formed in the polymer material by laser ablation, employing a sacrificial layer as a mask. Electroplated copper may be employed as a sacrificial release layer. One particular structure is a micromechanical electric switch including an array of individual switch contacts actuatable in common.
    Type: Grant
    Filed: January 4, 1993
    Date of Patent: December 20, 1994
    Assignee: General Electric Company
    Inventors: Mario Ghezzo, Richard J. Saia, Bharat S. Bagepalli, Imdad Imam, Dennis L. Polla
  • Patent number: 5367585
    Abstract: A microelectromechanical photonic switch includes first and second waveguides. Insulative cladding containing a gap and having a lower refractive index than the refractive indices of the first and second waveguides is situated between the first and second waveguides. One electrode comprising an at least partially transparent material is situated on the same side of the gap as the second waveguide. An additional electrode is provided either on the same side of the gap as the first waveguide or over a piezoelectric strip above a cladding layer on the second waveguide. At least one of the electrodes is capable of being advanced towards the other of the electrodes so as to cause one of the first and second waveguides to advance towards the other of the first and second waveguides.
    Type: Grant
    Filed: October 27, 1993
    Date of Patent: November 22, 1994
    Assignee: General Electric Company
    Inventors: Mario Ghezzo, Christopher P. Yakymyshyn, Richard J. Saia, Dennis L. Polla
  • Patent number: 5367584
    Abstract: A microelectromechanical photonic switching array comprises a plurality of first waveguides and a plurality of second waveguides. Insulative cladding is situated between the first and second waveguides. Each of the first waveguides is positioned with predetermined first waveguide portions on one side of at least one opening, and each of the second waveguides is positioned with predetermined second waveguide portions substantially parallel to respective ones of the predetermined first waveguide portions on an opposing side of said opening. A selected one of the predetermined second waveguide portions is capable of being moved closer and coupling light to a respective one of the predetermined first waveguide portions in response to either an electrostatic or piezoelectric signal. Alternatively, the first and second waveguides are co-planar and light is coupled from a predetermined first waveguide to a predetermined second waveguide by using a movable waveguide coupler.
    Type: Grant
    Filed: October 27, 1993
    Date of Patent: November 22, 1994
    Assignee: General Electric Company
    Inventors: Mario Ghezzo, Christopher P. Yakymyshyn, Anil R. Duggal
  • Patent number: 4707455
    Abstract: A method of fabricating a semiconductor device having a symmetric and complementary P-well and N-well. The novel method involves the introduction of a first dopant type into a semiconductor substrate directly through those regions of an oxide layer and a nitride layer which do not underlie a first mask layer. The first mask layer is removed and a second mask layer is formed. A complementary dopant type is then introduced into the semiconductor substrate directly through those regions of the oxide layer and nitride layer which do not underlie the second mask layer. The second mask layer is removed and the dopant ions are simultaneously subjected to thermal drive in to thereby form adjacent wells of opposite dopant type in the semiconductor substrate.
    Type: Grant
    Filed: November 26, 1986
    Date of Patent: November 17, 1987
    Assignee: General Electric Company
    Inventors: Joseph C. Tsang, Mario Ghezzo, Robert T. Fuller
  • Patent number: 4583281
    Abstract: A method of forming in a silicon substrate an active region bounded by a field of silicon dioxide is described. On top of a mesa formed in the silicon substrate is provided a three layered structure including a first thin layer of silicon dioxide in contact with the top of the mesa, a second thicker layer of silicon nitride overlying the thin layer of silicon dioxide and a third layer of silicon dioxide overlying the layer of silicon nitride. A further layer of silicon nitride is formed over the three layered structure and the exposed surfaces of the silicon substrate. Spacer portions of silicon nitride are formed on the sides of the mesa and the three layered structure by anisotropically etching the fourth layer of silicon nitride. By controlling the thicknesses of the first, second and third layers, the width of the spacer portions is optimized to prevent lateral oxidation of the active region.
    Type: Grant
    Filed: March 13, 1985
    Date of Patent: April 22, 1986
    Assignee: General Electric Company
    Inventors: Mario Ghezzo, Manjin J. Kim
  • Patent number: 4528582
    Abstract: End portions of a polycrystalline silicon resistor are bonded to conductive members of silicon of low resistivity through a silicide of a suitable metal such as platinum.
    Type: Grant
    Filed: September 21, 1983
    Date of Patent: July 9, 1985
    Assignee: General Electric Company
    Inventors: Simon S. Cohen, Mario Ghezzo