Patents by Inventor Mario J. Interrante

Mario J. Interrante has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6216937
    Abstract: A process and apparatus for removing flip chips with C4 joints mounted on a multi-chip module by applying a tensile force to one or more removal member bonded to the back of one or more flip chips during heating of the module to a temperature sufficient to cause the C4 joints to become molten. The tensile force can either be a compressed spring, or a bimetallic member which is flat at room temperature and becomes curved when heated to such temperature, or a memory alloy whose original shape is curved and which is bent flat at room temperature but returns to its original curved shape when heated to such temperature. An adhesive is used to bond the removal member to the chip to be removed and is a low temperature, fast curing adhesive with high temperature tolerance after curing.
    Type: Grant
    Filed: December 22, 1999
    Date of Patent: April 17, 2001
    Assignee: International Business Machines Corporation
    Inventors: Stephen A. DeLaurentis, Mario J. Interrante, Raymond A. Jackson, John U. Knickerbocker, Sudipta K. Ray, Kathleen A. Stalter
  • Patent number: 6158644
    Abstract: This invention relates to a solder structure which provides enhanced fatigue life properties when used to bond substrates particularly at the second level such as BGA and CGA interconnections. The solder structure is preferably a sphere or column and has a metal layer wettable by solder and the structure is used to make solder connections in electronic components such as joining an electronic module such as a chip connected to a MLC which module is connected to a circuit board. The solder structure preferably has an overcoat of solder on the metal layer to provide a passivation coating to the metal layer to keep it clean from oxidation and corrosion and also provide a wettable surface for attachment of the solder structure to solder on the pads of the substrate being bonded.
    Type: Grant
    Filed: April 30, 1998
    Date of Patent: December 12, 2000
    Assignee: International Business Machines Corporation
    Inventors: Peter J. Brofman, Mark G. Courtney, Shaji Farooq, Mario J. Interrante, Raymond A. Jackson, Gregory B. Martin, Sudipta K. Ray, William E. Sablinski, Kathleen A. Stalter
  • Patent number: 6037193
    Abstract: The present invention relates generally to a new process for hermetically sealing of a high thermally conductive substrate, such as, an aluminum nitride substrate, using a low thermally conductive interposer and structure thereof. More particularly, the invention encompasses a hermetic cap which is secured to an aluminum nitride substrate using the novel thermal interposer. The novel thermal interposer basically comprises of layers of relatively high thermal conductive metallic materials sandwiching a core layer of low thermal conductive metallic material.
    Type: Grant
    Filed: January 31, 1997
    Date of Patent: March 14, 2000
    Assignee: International Business Machines Corporation
    Inventors: Mario J. Interrante, Laertis Economikos, Lester Wynn Herron
  • Patent number: 5990418
    Abstract: A device and method for hermetically sealing an integrated circuit chip between a substrate and a lid while providing effective dissipation of heat generated by the integrated circuit chip. The device includes an integrated circuit chip, carrier substrate, interface coolant, and a lid. The integrated circuit chip is attached to the top of the carrier substrate. The interface coolant is disposed on the top of the integrated circuit chip and the lid is placed on top of the carrier substrate/integrated circuit chip combination and contacts the interface coolant. The interface coolant provides a thermal path for conducting heat from the integrated circuit chip to the lid. The substrate is attached to a circuit board by a ceramic ball grid array (CBGA) or a ceramic column grid array (CCGA).
    Type: Grant
    Filed: July 29, 1997
    Date of Patent: November 23, 1999
    Assignee: International Business Machines Corporation
    Inventors: Kevin G. Bivona, Jeffrey T. Coffin, Stephen S. Drofitz, Jr., Lewis S. Goldmann, Mario J. Interrante, Sushumna Iruvanti, Raed A. Sherif
  • Patent number: 5945735
    Abstract: The present invention relates generally to a new process for hermetically sealing of a high thermally conductive substrate, such as, an aluminum nitride substrate, using a low thermally conductive interposer and structure thereof. More particularly, the invention encompasses a hermetic cap which is secured to an aluminum nitride substrate using the novel thermal interposer. The novel thermal interposer basically comprises of layers of relatively high thermal conductive metallic materials sandwiching a core layer of low thermal conductive metallic material.
    Type: Grant
    Filed: January 31, 1997
    Date of Patent: August 31, 1999
    Assignee: International Business Machines Corporation
    Inventors: Laertis Economikos, Lester Wynn Herron, Mario J. Interrante
  • Patent number: 5543584
    Abstract: The present invention relates generally to a new method of repairing electrical lines, and more particularly to repairing electrical lines having an opening at the module level with devices in place. Various methods and processes are used to repair this open or defective portion in an electrical conductor line. It could be repaired by securing a jumper wire or nugget across the open or the repair could be made by a deposition process, which includes but is not limited to filling the opening with a solder type material or inserting a solder coated electrical wire and heating the solder and allowing the solder to melt and repair the open. One of the attributes of this invention is the ability to repair on a substrate or module on which active components such as chips, and passive components such as pins, capacitors, etc. have been attached. The invention also allows repair of fine line patterns which are normally not repairable by conventional techniques.
    Type: Grant
    Filed: February 28, 1992
    Date of Patent: August 6, 1996
    Assignee: International Business Machines Corporation
    Inventors: Edward F. Handford, Joseph M. Harvilchuck, Mario J. Interrante, Raymond A. Jackson, Raj N. Master, Sudipta K. Ray, William E. Sablinski, Thomas A. Wassick
  • Patent number: 5478009
    Abstract: A solder ball removal tool uses ultrasonic vibrations to remove specific solder balls from high density chips, substrate solder ball terminal connections, card or board solder ball connections, or other solder ball array for the purpose of customizing the electrical functionality of a module. The tool also allows for the removal of damaged or defective solder balls for the purpose of replacement with defect free solder balls.
    Type: Grant
    Filed: August 10, 1994
    Date of Patent: December 26, 1995
    Assignee: International Business Machines Corporation
    Inventors: Mario J. Interrante, Laertis Economikos
  • Patent number: 5425493
    Abstract: A specially designed tip containing an electron discharge milled cone of specific dimensions is used to transfer a critical solder volume from a solder ball carrier to a specific solder ball site on the base line metal on a high density chip, substrate terminal connection, solder ball connection, or any solder ball array. The critical tip/cone dimensions have a height of the cone and a circumference at the base which generate a specific volume of solder to be transferred.
    Type: Grant
    Filed: August 10, 1994
    Date of Patent: June 20, 1995
    Assignee: International Business Machines Corporation
    Inventors: Mario J. Interrante, Laertis Economikos
  • Patent number: 5288007
    Abstract: The present invention relates generally to apparatus and methods for making simultaneous electrical connections, and more particularly to making these electrical connections simultaneously using a new bond tip configuration. Various methods and processes are being disclosed to simultaneously make electrical connections between electrical conductor lines or pads. The electrical connection is made by placing an electrically conductive wire across a pair of electrical lines or pads that have to be electrically connected and then by using a special tip, both ends of the electrically conductive wire are simultaneously secured to the two electrically conductive lines or pads.
    Type: Grant
    Filed: December 23, 1992
    Date of Patent: February 22, 1994
    Assignee: International Business Machine Corporation
    Inventors: Mario J. Interrante, Michael Berger, Edward F. Handford, Eugene Tas
  • Patent number: 5243140
    Abstract: A direct distribution wiring system is provided which facilitates the effecting of repair or engineering change in a Multi-chip module (MCM) while eliminating the need for redistribution and/or buried connections between IC attachment pads and engineering change pads, thus eliminating the need for patterned conductor layers corresponding to such functions. The operation of the MCM is improved by the wiring system allowing the reduction of lumped capacitances by disconnection of defective conductors, accomplished by providing severable connectors in a direct distribution structure, as well as the elimination of redistribution wiring layers and increased IC density on the MCM. Full potential fault coverage as well as full discretion in reversible engineering changes is provided by forming all elements of the wiring system on the surface of the device.
    Type: Grant
    Filed: October 4, 1991
    Date of Patent: September 7, 1993
    Assignee: International Business Machines Corporation
    Inventors: Harsaran S. Bhatia, Mario J. Interrante, Suresh D. Kadakia, Shashi D. Malaviya, Mark H. McLeod, Sudipta K. Ray, Herbert I. Stoller
  • Patent number: 5193732
    Abstract: The present invention relates generally to apparatus and methods for making simultaneous electrical connections, and more particularly to making these electrical connections simultaneously using a new bond tip configuration. Various methods and processes are being disclosed to simultaneously make electrical connections between electrical conductor lines or pads. The electrical connection is made by placing an electrically conductive wire across a pair of electrical lines or pads that have to be electrically connected and then by using a special tip, both ends of the electrically conductive wire are simultaneously secured to the two electrically conductive lines or pads.
    Type: Grant
    Filed: October 4, 1991
    Date of Patent: March 16, 1993
    Assignee: International Business Machines Corporation
    Inventors: Mario J. Interrante, Michael Berger, Edward F. Handford, Eugene Tas
  • Patent number: 5153408
    Abstract: The present invention relates generally to a new method of repairing electrical lines, and more praticularly to repairing electrical lines having an open at the module level with devices in place. Various methods and processes are used to repair this open or defective portion in an electrical conductor line. It could be repaired by securing a jumper wire or nugget across the open or the repair could be made by a deposition process, which includes but is not limited to filling the open with a solder type material or inserting a solder coated electrical wire and heating the solder and allowing the solder to melt and repair the open. One of the attributes of this invention is the ability to repair on a substrate or module on which active components such as chips, and passive components such as pins, capacitors, etc. have been attached. The invention also allows repair of fine line patterns which are normally not repairable by conventional techniques.
    Type: Grant
    Filed: October 31, 1990
    Date of Patent: October 6, 1992
    Assignee: International Business Machines Corporation
    Inventors: Edward F. Handford, Joseph M. Harvilchuck, Mario J. Interrante, Raymond A. Jackson, Raj N. Master, Sudipta K. Ray, William E. Sablinski, Thomas A. Wassick
  • Patent number: 4634638
    Abstract: Brazing of elements to electronic chip carrying substrates requires brazing materials strong at high temperatures used to remove and replace chips. Flanges and pins are brazed with Au:Sn brazing alloys modified during brazing by addition of copper to the brazing material to promote formation of the higher melting point .beta. phase of the alloy and a Group VIII metal to draw Sn out of the melt by gettering, also to promote formation of the .beta. phase of the alloy and to thicken the braze material. A copper preform is plated with Ni and juxtaposed with surfaces to be brazed and the brazing material to add Ni and copper to the melt.
    Type: Grant
    Filed: December 17, 1981
    Date of Patent: January 6, 1987
    Assignee: International Business Machines Corporation
    Inventors: Norman G. Ainslie, Joseph M. Harvilchuck, Mario J. Interrante, William J. King, Jr., Paul H. Palmateer, John F. Sullivan