Patents by Inventor Mario Jesus Martinez
Mario Jesus Martinez has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230385192Abstract: A memory module comprises dynamic random access memory (DRAM), Flash memory, and a module controller. The module controller is configured to receive data to be transferred from the DRAM to the Flash memory, compute first cyclic redundancy check (CRC) codes for the data, and write the data into the Flash memory. The module controller is further configured to read the data from the Flash memory, compute second CRC codes for the data read from the Flash memory, and transfer the data to the DRAM. The module controller is further configured to compare the second CRC codes with the first CRC codes to determine one or more erroneous data bits in the data read from the Flash memory, read a data segment of the data from the DRAM that include the one or more erroneous data bits, correct the one or more erroneous data bits in the data segment, and write the data segment back into the DRAM.Type: ApplicationFiled: May 29, 2023Publication date: November 30, 2023Inventors: Hyun Lee, Jayesh R. Bhakta, Chi She Chen, Jeffery C. Solomon, Mario Jesus Martinez, Hao Le, Soon J. Choi
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Patent number: 11663121Abstract: A memory module comprises a volatile memory subsystem including DRAM, a non-volatile memory subsystem including Flash memory, and a module control device. The Flash memory includes main Flash providing a main Flash memory space and scratch Flash providing a scratch Flash memory space. The module control device is configured to receive a request from the memory controller to move one or more segments of data in a first Flash block in the main Flash to the DRAM and to, for each respective segment of data: select a respective set of pages in the DRAM; transfer respective data stored in the respective set of pages from the DRAM to a corresponding segment in the scratch Flash; and transfer the respective segment of data to the respective set of pages in the DRAM. Thus, data can be moved segment by segment between the DRAM and the Flash memory.Type: GrantFiled: November 20, 2021Date of Patent: May 30, 2023Assignee: Netlist, Inc.Inventors: Hyun Lee, Jayesh R. Bhakta, Chi She Chen, Jeffery C. Solomon, Mario Jesus Martinez, Hao Le, Soon J. Choi
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Publication number: 20220253380Abstract: A memory module comprises a volatile memory subsystem including DRAM, a non-volatile memory subsystem including Flash memory, and a module control device. The Flash memory includes main Flash providing a main Flash memory space and scratch Flash providing a scratch Flash memory space. The module control device is configured to receive a request from the memory controller to move one or more segments of data in a first Flash block in the main Flash to the DRAM and to, for each respective segment of data: select a respective set of pages in the DRAM; transfer respective data stored in the respective set of pages from the DRAM to a corresponding segment in the scratch Flash; and transfer the respective segment of data to the respective set of pages in the DRAM. Thus, data can be moved segment by segment between the DRAM and the Flash memory.Type: ApplicationFiled: November 20, 2021Publication date: August 11, 2022Inventors: Hyun Lee, Jayesh R. Bhakta, Chi She Chen, Jeffery C. Solomon, Mario Jesus Martinez, Hao Le, Soon J. Choi
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Patent number: 11243886Abstract: A memory module comprises a volatile memory subsystem configured to coupled to a memory channel in computer system and capable of serving as main memory for the computer system, a non-volatile memory subsystem providing storage for the computer system, and a module controller coupled to the volatile memory subsystem, the non-volatile memory subsystem, and the C/A bus. The module controller is configured to control intra-module data transfers between the volatile memory subsystem and the non-volatile memory subsystem. The module controller is further configured to monitor C/A signals on the C/A bus and schedule the intra-module data transfers in accordance with the C/A signals so that the intra-module data transfers do not conflict with accesses to the volatile memory subsystem by the memory controller.Type: GrantFiled: August 13, 2019Date of Patent: February 8, 2022Assignee: Netlist, Inc.Inventors: Hyun Lee, Jayesh R Bhakta, Chi She Chen, Jeffery C. Solomon, Mario Jesus Martinez, Hao Le, Soon J. Choi
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Publication number: 20200042456Abstract: A memory module comprises a volatile memory subsystem configured to coupled to a memory channel in computer system and capable of serving as main memory for the computer system, a non-volatile memory subsystem providing storage for the computer system, and a module controller coupled to the volatile memory subsystem, the non-volatile memory subsystem, and the C/A bus. The module controller is configured to control intra-module data transfers between the volatile memory subsystem and the non-volatile memory subsystem. The module controller is further configured to monitor C/A signals on the C/A bus and schedule the intra-module data transfers in accordance with the C/A signals so that the intra-module data transfers do not conflict with accesses to the volatile memory subsystem by the memory controller.Type: ApplicationFiled: August 13, 2019Publication date: February 6, 2020Inventors: Hyun Lee, Jayesh R. Bhakta, Chi She Chen, Jeffery C. Solomon, Mario Jesus Martinez, Hao Le, Soon J. Choi
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Patent number: 10380022Abstract: A memory module comprises a volatile memory subsystem configured to coupled to a memory channel in computer system and capable of serving as main memory for the computer system, a non-volatile memory subsystem providing storage for the computer system, and a module controller coupled to the volatile memory subsystem, the non-volatile memory subsystem, and the C/A bus. The module controller is configured to control intra-module data transfers between the volatile memory subsystem and the non-volatile memory subsystem. The module controller is further configured to monitor C/A signals on the C/A bus and schedule the intra-module data transfers in accordance with the C/A signals so that the intra-module data transfers do not conflict with accesses to the volatile memory subsystem by the memory controller.Type: GrantFiled: November 7, 2014Date of Patent: August 13, 2019Assignee: Netlist, Inc.Inventors: Hyun Lee, Jayesh R. Bhakta, Chi She Chen, Jeffery C. Solomon, Mario Jesus Martinez, Hao Le, Soon J. Choi
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Patent number: 10025731Abstract: Certain embodiments described herein include a memory module having a printed circuit board including at least one connector configured to be operatively coupled to a memory controller of a computer system. The memory module further includes a plurality of memory devices on the printed circuit board and a circuit including a first set of ports operatively coupled to at least one memory device. The circuit further includes a second set of ports operatively coupled to the at least one connector. The circuit includes a switching circuit configured to selectively operatively couple one or more ports of the second set of ports to one or more ports of the first set of ports. Each port of the first set and the second set comprises a correction circuit which reduces noise in one or more signals transmitted between the first set of ports and the second set of ports.Type: GrantFiled: May 18, 2015Date of Patent: July 17, 2018Assignee: NETLIST, INC.Inventors: Hyun Lee, Jayesh R. Bhakta, Jeffrey C. Solomon, Mario Jesus Martinez, Chi-She Chen
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Patent number: 9846659Abstract: Certain embodiments described herein include a memory module having a printed circuit board including at least one connector configured to be operatively coupled to a memory controller of a computer system. The memory module further includes a plurality of memory devices on the printed circuit board and a circuit including a first set of ports operatively coupled to at least one memory device. The circuit further includes a second set of ports operatively coupled to the at least one connector. The circuit includes a switching circuit configured to selectively operatively couple one or more ports of the second set of ports to one or more ports of the first set of ports. Each port of the first set and the second set comprises a correction circuit which reduces noise in one or more signals transmitted between the first set of ports and the second set of ports.Type: GrantFiled: May 18, 2015Date of Patent: December 19, 2017Assignee: Netlist, Inc.Inventors: Hyun Lee, Jayesh R. Bhakta, Jeffrey C. Solomon, Mario Jesus Martinez, Chi-She Chen
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Publication number: 20150169238Abstract: A memory module comprises a volatile memory subsystem configured to coupled to a memory channel in computer system and capable of serving as main memory for the computer system, a non-volatile memory subsystem providing storage for the computer system, and a module controller coupled to the volatile memory subsystem, the non-volatile memory subsystem, and the C/A bus. The module controller is configured to control intra-module data transfers between the volatile memory subsystem and the non-volatile memory subsystem. The module controller is further configured to monitor C/A signals on the C/A bus and schedule the intra-module data transfers in accordance with the C/A signals so that the intra-module data transfers do not conflict with accesses to the volatile memory subsystem by the memory controller.Type: ApplicationFiled: November 7, 2014Publication date: June 18, 2015Inventors: Hyun Lee, Jayesh R. Bhakta, Chi She Chen, Jeffery C. Solomon, Mario Jesus Martinez, Hao Le, Soon J. Choi
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Patent number: 9037809Abstract: Certain embodiments described herein include a memory module having a printed circuit board including at least one connector configured to be operatively coupled to a memory controller of a computer system. The memory module further includes a plurality of memory devices on the printed circuit board and a circuit including a first set of ports operatively coupled to at least one memory device. The circuit further includes a second set of ports operatively coupled to the at least one connector. The circuit includes a switching circuit configured to selectively operatively couple one or more ports of the second set of ports to one or more ports of the first set of ports. Each port of the first set and the second set comprises a correction circuit which reduces noise in one or more signals transmitted between the first set of ports and the second set of ports.Type: GrantFiled: July 7, 2014Date of Patent: May 19, 2015Assignee: Netlist, Inc.Inventors: Hyun Lee, Jayesh R. Bhakta, Jeffrey C. Solomon, Mario Jesus Martinez, Chi-She Chen
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Patent number: 8782350Abstract: Certain embodiments described herein include a memory module having a printed circuit board including at least one connector configured to be operatively coupled to a memory controller of a computer system. The memory module further includes a plurality of memory devices on the printed circuit board and a circuit including a first set of ports operatively coupled to at least one memory device. The circuit further includes a second set of ports operatively coupled to the at least one connector. The circuit includes a switching circuit configured to selectively operatively couple one or more ports of the second set of ports to one or more ports of the first set of ports. Each port of the first set and the second set comprises a correction circuit which reduces noise in one or more signals transmitted between the first set of ports and the second set of ports.Type: GrantFiled: March 5, 2012Date of Patent: July 15, 2014Assignee: Netlist, Inc.Inventors: Hyun Lee, Jayesh R. Bhakta, Jeffrey C. Solomon, Mario Jesus Martinez, Chi-She Chen
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Publication number: 20120250386Abstract: Certain embodiments described herein include a memory module having a printed circuit board including at least one connector configured to be operatively coupled to a memory controller of a computer system. The memory module further includes a plurality of memory devices on the printed circuit board and a circuit including a first set of ports operatively coupled to at least one memory device. The circuit further includes a second set of ports operatively coupled to the at least one connector. The circuit includes a switching circuit configured to selectively operatively couple one or more ports of the second set of ports to one or more ports of the first set of ports. Each port of the first set and the second set comprises a correction circuit which reduces noise in one or more signals transmitted between the first set of ports and the second set of ports.Type: ApplicationFiled: March 5, 2012Publication date: October 4, 2012Applicant: NETLIST, INC.Inventors: Hyun Lee, Jayesh R. Bhakta, Jeffrey C. Solomon, Mario Jesus Martinez, Chi-She Chen
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Patent number: 8154901Abstract: Certain embodiments described herein include a memory module having a printed circuit board including at least one connector configured to be operatively coupled to a memory controller of a computer system. The memory module further includes a plurality of memory devices on the printed circuit board and a circuit including a first set of ports operatively coupled to at least one memory device. The circuit further includes a second set of ports operatively coupled to the at least one connector. The circuit includes a switching circuit configured to selectively operatively couple one or more ports of the second set of ports to one or more ports of the first set of ports. Each port of the first set and the second set comprises a correction circuit which reduces noise in one or more signals transmitted between the first set of ports and the second set of ports.Type: GrantFiled: April 13, 2009Date of Patent: April 10, 2012Assignee: Netlist, Inc.Inventors: Hyun Lee, Jayesh R. Bhakta, Jeffrey C. Solomon, Mario Jesus Martinez, Chi-She Chen