Patents by Inventor Mario MAIORE

Mario MAIORE has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11740136
    Abstract: A circuit includes a first input terminal, a second input terminal, a third input terminal and an output terminal. A first summation node adds signals at the first and third input terminals. A second summation node subtracts signals at the second and third input terminals. A selector selects between the added signals and subtracted signals in response to a selection signal. The output of the selector is integrated to generate an integrated signal. The integrated signal is compared by a comparator to a threshold, the comparator generating an output signal at the output terminal having a first level and a second level. Feedback of the output signal produces the selection signal causing the selector to select the added signals in response to the first level of the output signal and causing the selector to select the subtracted signals in response to the second level of the output signal.
    Type: Grant
    Filed: September 3, 2020
    Date of Patent: August 29, 2023
    Assignee: STMicroelectronics S.r.l.
    Inventors: Michele Vaiana, Paolo Pesenti, Mario Chiricosta, Calogero Marco Ippolito, Mario Maiore
  • Publication number: 20220416743
    Abstract: A circuit includes an amplifier, a bias voltage node, and a first set of switches configured, based on a first reset signal having a first value, to couple first and second input nodes to the bias voltage node and to couple first and second output nodes of the amplifier. First and second feedback branches each include a respective RC network including a plurality of capacitances. The first and second feedback branches further include a second set of switches intermediate input nodes and the capacitances, and a third set of switches intermediate input nodes and the plurality of capacitances. These switches selectively couple the capacitances to the input nodes and output nodes, based on a second reset signal having a first value. The second reset signal keeps the first value for a determined time interval exceeding a time interval in which the first reset signal has the first value.
    Type: Application
    Filed: June 13, 2022
    Publication date: December 29, 2022
    Applicant: STMicroelectronics S.r.l.
    Inventors: Roberto MODAFFARI, Paolo PESENTI, Mario MAIORE, Tiziano CHIARILLO
  • Publication number: 20200400507
    Abstract: A circuit includes a first input terminal, a second input terminal, a third input terminal and an output terminal. A first summation node adds signals at the first and third input terminals. A second summation node subtracts signals at the second and third input terminals. A selector selects between the added signals and subtracted signals in response to a selection signal. The output of the selector is integrated to generate an integrated signal. The integrated signal is compared by a comparator to a threshold, the comparator generating an output signal at the output terminal having a first level and a second level. Feedback of the output signal produces the selection signal causing the selector to select the added signals in response to the first level of the output signal and causing the selector to select the subtracted signals in response to the second level of the output signal.
    Type: Application
    Filed: September 3, 2020
    Publication date: December 24, 2020
    Applicant: STMicroelectronics S.r.l.
    Inventors: Michele VAIANA, Paolo PESENTI, Mario CHIRICOSTA, Calogero Marco IPPOLITO, Mario MAIORE
  • Patent number: 10794772
    Abstract: A circuit includes a first input terminal, a second input terminal, a third input terminal and an output terminal. A first summation node adds signals at the first and third input terminals. A second summation node subtracts signals at the second and third input terminals. A selector selects between the added signals and subtracted signals in response to a selection signal. The output of the selector is integrated to generate an integrated signal. The integrated signal is compared by a comparator to a threshold, the comparator generating an output signal at the output terminal having a first level and a second level. Feedback of the output signal produces the selection signal causing the selector to select the added signals in response to the first level of the output signal and causing the selector to select the subtracted signals in response to the second level of the output signal.
    Type: Grant
    Filed: April 20, 2018
    Date of Patent: October 6, 2020
    Assignee: STMicroelectronics S.r.l.
    Inventors: Michele Vaiana, Paolo Pesenti, Mario Chiricosta, Calogero Marco Ippolito, Mario Maiore
  • Publication number: 20180313699
    Abstract: A circuit includes a first input terminal, a second input terminal, a third input terminal and an output terminal. A first summation node adds signals at the first and third input terminals. A second summation node subtracts signals at the second and third input terminals. A selector selects between the added signals and subtracted signals in response to a selection signal. The output of the selector is integrated to generate an integrated signal. The integrated signal is compared by a comparator to a threshold, the comparator generating an output signal at the output terminal having a first level and a second level. Feedback of the output signal produces the selection signal causing the selector to select the added signals in response to the first level of the output signal and causing the selector to select the subtracted signals in response to the second level of the output signal.
    Type: Application
    Filed: April 20, 2018
    Publication date: November 1, 2018
    Applicant: STMicroelectronics S.r.l.
    Inventors: Michele VAIANA, Paolo PESENTI, Mario CHIRICOSTA, Calogero Marco IPPOLITO, Mario MAIORE
  • Patent number: 9540229
    Abstract: A packaged sensor assembly includes: a packaging structure, having at least one opening; a humidity sensor and a pressure sensor, which are housed inside the packaging structure and communicate fluidically with the outside through the opening, and a control circuit, operatively coupled to the humidity sensor and to the pressure sensor; wherein the humidity sensor and the control circuit are integrated in a first chip, and the pressure sensor is integrated in a second chip distinct from the first chip and bonded to the first chip.
    Type: Grant
    Filed: December 8, 2015
    Date of Patent: January 10, 2017
    Assignee: STMicroelectronics S.r.l.
    Inventors: Giuseppe Bruno, Sebastiano Conti, Mario Chiricosta, Michele Vaiana, Calogero Marco Ippolito, Mario Maiore, Daniele Casella
  • Patent number: 9534974
    Abstract: A pressure sensor includes a body made of semiconductor material having a first type of conductivity and a pressure-sensitive structure having the first type of conductivity defining a suspended membrane. One or more piezoresistive elements having a second type of conductivity (P) are formed in the suspended membrane. The piezoresistive elements form, with the pressure-sensitive structure, respective junction diodes. A temperature sensing method includes: generating a first current between conduction terminals common to the junction diodes; detecting a first voltage value between the common conduction terminals when the first current is supplied; and correlating the detected first voltage value to a value of temperature of the diodes. The temperature value thus calculated can be used for correcting the voltage signal generated at output by the pressure sensor when the latter is operated for sensing an applied outside pressure which deforms the suspended membrane.
    Type: Grant
    Filed: February 1, 2013
    Date of Patent: January 3, 2017
    Assignee: STMICROELECTRONICS S.R.L.
    Inventors: Michele Vaiana, Mario Chiricosta, Mario Maiore, Lorenzo Baldo, Paul Georges Marie Rose
  • Patent number: 9518886
    Abstract: A pressure sensor includes a body made of semiconductor material having a first type of conductivity and a pressure-sensitive structure having the first type of conductivity defining a suspended membrane. One or more piezoresistive elements having a second type of conductivity (P) are formed in the suspended membrane. The piezoresistive elements form, with the pressure-sensitive structure, respective junction diodes. A temperature sensing method includes: generating a first current between conduction terminals common to the junction diodes; detecting a first voltage value between the common conduction terminals when the first current is supplied; and correlating the detected first voltage value to a value of temperature of the diodes. The temperature value thus calculated can be used for correcting the voltage signal generated at output by the pressure sensor when the latter is operated for sensing an applied outside pressure which deforms the suspended membrane.
    Type: Grant
    Filed: November 24, 2015
    Date of Patent: December 13, 2016
    Assignee: STMicroelectronics S.r.l.
    Inventors: Lorenzo Baldo, Michele Vaiana, Mario Chiricosta, Mario Maiore, Paul Georges Marie Rose
  • Publication number: 20160347606
    Abstract: A packaged sensor assembly includes: a packaging structure, having at least one opening; a humidity sensor and a pressure sensor, which are housed inside the packaging structure and communicate fluidically with the outside through the opening, and a control circuit, operatively coupled to the humidity sensor and to the pressure sensor; wherein the humidity sensor and the control circuit are integrated in a first chip, and the pressure sensor is integrated in a second chip distinct from the first chip and bonded to the first chip.
    Type: Application
    Filed: December 8, 2015
    Publication date: December 1, 2016
    Inventors: Giuseppe BRUNO, Sebastiano CONTI, Mario CHIRICOSTA, Michele VAIANA, Calogero Marco IPPOLITO, Mario MAIORE, Daniele CASELLA
  • Publication number: 20160076962
    Abstract: A pressure sensor includes a body made of semiconductor material having a first type of conductivity and a pressure-sensitive structure having the first type of conductivity defining a suspended membrane. One or more piezoresistive elements having a second type of conductivity (P) are formed in the suspended membrane. The piezoresistive elements form, with the pressure-sensitive structure, respective junction diodes. A temperature sensing method includes: generating a first current between conduction terminals common to the junction diodes; detecting a first voltage value between the common conduction terminals when the first current is supplied; and correlating the detected first voltage value to a value of temperature of the diodes. The temperature value thus calculated can be used for correcting the voltage signal generated at output by the pressure sensor when the latter is operated for sensing an applied outside pressure which deforms the suspended membrane.
    Type: Application
    Filed: November 24, 2015
    Publication date: March 17, 2016
    Applicant: STMicroelectronics S.r.l.
    Inventors: Lorenzo Baldo, Michele Vaiana, Mario Chiricosta, Mario Maiore, Paul Georges Marie Rose
  • Patent number: 9071260
    Abstract: An embodiment of a circuit includes an input node, a generator, a combiner, a converter, and a filter. The input node is configured to receive an input signal in a first domain, and the generator is configured to generate a periodic signal in the first domain. The combiner is configured to combine the input and periodic signals into a resulting signal in the first domain, and the converter is configured to convert the resulting signal into a converted signal in a second domain. And the filter is configured to remove from the converted signal substantially all of a frequency component of the converted signal having substantially a same frequency as a frequency component of the periodic signal.
    Type: Grant
    Filed: July 30, 2014
    Date of Patent: June 30, 2015
    Assignee: STMicroelectronics S.r.l.
    Inventors: Mario Chiricosta, Calogero Marco Ippolito, Mario Maiore, Orlando Peluso, Michele Vaiana
  • Publication number: 20150035691
    Abstract: An embodiment of a circuit includes an input node, a generator, a combiner, a converter, and a filter. The input node is configured to receive an input signal in a first domain, and the generator is configured to generate a periodic signal in the first domain. The combiner is configured to combine the input and periodic signals into a resulting signal in the first domain, and the converter is configured to convert the resulting signal into a converted signal in a second domain. And the filter is configured to remove from the converted signal substantially all of a frequency component of the converted signal having substantially a same frequency as a frequency component of the periodic signal.
    Type: Application
    Filed: July 30, 2014
    Publication date: February 5, 2015
    Inventors: Mario CHIRICOSTA, Calogero Marco IPPOLITO, Mario MAIORE, Orlando PELUSO, Michele VAIANA