Patents by Inventor Mario Montana

Mario Montana has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7082071
    Abstract: An integrated circuit chip includes a plurality of independent FIFO memory devices that are each configured to support all four combinations of DDR and SDR write modes and DDR and SDR read modes and collectively configured to support all four multiplexer, demultiplexer, broadcast and multi-Q operating modes.
    Type: Grant
    Filed: June 30, 2004
    Date of Patent: July 25, 2006
    Assignee: Integrated Device Technology, Inc.
    Inventors: Roland T. Knaack, David Stuart Gibson, Mario Montana, Mario Au, Stewart Speed, Srinivas Satish Babu Bamdhamravuri, Uksong Kang
  • Patent number: 6907479
    Abstract: Integrated circuit FIFO memory devices may be controlled using a register file, an indexer and a controller. The FIFO memory device includes a FIFO memory that is divisible into up to a predetermined number of independent FIFO queues. The register file includes the predetermined number of words. A respective word is configured to store one or more parameters for a respective one of the FIFO queues. The indexer is configured to index into the register file, to access a respective word that corresponds to a respective FIFO queue that is accessed. The controller is responsive to the respective word that is accessed, and is configured to control access to the respective FIFO queue based upon at least one of the one or more parameters that is stored in the respective word. Thus, as the number of FIFO queues expands, the number of words in the register file may need to expand, but the controller and/or indexer need not change substantially.
    Type: Grant
    Filed: August 30, 2001
    Date of Patent: June 14, 2005
    Assignee: Integrated Device Technology, Inc.
    Inventors: Curt A. Karnstedt, Bruce L. Chin, Prashant Shamarao, Mario Montana
  • Publication number: 20050018514
    Abstract: An integrated circuit chip includes a plurality of independent FIFO memory devices that are each configured to support all four combinations of DDR and SDR write modes and DDR and SDR read modes and collectively configured to support all four multiplexer, demultiplexer, broadcast and multi-Q operating modes.
    Type: Application
    Filed: June 30, 2004
    Publication date: January 27, 2005
    Inventors: Roland Knaack, David Gibson, Mario Montana, Mario Au, Stewart Speed, Srinivas Bamdhamravuri, Uksong Kang
  • Publication number: 20030018862
    Abstract: Integrated circuit FIFO memory devices may be controlled using a register file, an indexer and a controller. The FIFO memory device includes a FIFO memory that is divisible into up to a predetermined number of independent FIFO queues. The register file includes the predetermined number of words. A respective word is configured to store one or more parameters for a respective one of the FIFO queues. The indexer is configured to index into the register file, to access a respective word that corresponds to a respective FIFO queue that is accessed. The controller is responsive to the respective word that is accessed, and is configured to control access to the respective FIFO queue based upon at least one of the one or more parameters that is stored in the respective word. Thus, as the number of FIFO queues expands, the number of words in the register file may need to expand, but the controller and/or indexer need not change substantially.
    Type: Application
    Filed: August 30, 2001
    Publication date: January 23, 2003
    Inventors: Curt A. Karnstedt, Bruce L. Chin, Prashant Shamarao, Mario Montana