Abstract: A logic circuit with improved performance when operating at the limits of the transistor's bandwidth. In particular, a latch includes a clocked trans-admittance stage circuit for receiving a voltage and producing a current output, and an active load, such as a trans-impedance stage circuit, connected to receive as input the current output of the trans-admittance stage circuit and produce a voltage output. Two independent trans-admittance and trans-impedance stages may be combined as a single latch pair. One or more latch pairs may be arranged in series as a cascaded chain and connected to the output current of a clocked trans-admittance stage latch.

Abstract: A circuit for generating a digital data signal from an analog input data signal is disclosed. The circuit comprises a master-slave flip-flop with a clock input for receiving the analog input data signal, an amplitude detecting circuit for detecting the amplitude of the analog input data signal and generating an amplitude detection signal in response thereto, and a phase shifting circuit responsive to the amplitude detection signal for supplying a phase shifted signal to the clock input of the master-slave flip-flop. The circuit may further include a clock recovery circuit for generating a recovered clock signal from a clock signal contained in the analog input data signal. The recovered clock signal may be supplied to the amplitude detecting circuit, or a feedback loop may supply the phase shifted clock signal to the amplitude detecting circuit.

Abstract: A latch chain having improved input voltage sensitivity. The chain includes a first latch, an amplifier, and a second latch connected in series. The second latch is a conventional latch. The first latch is modified to have a higher sensitivity and lower output voltage swing than conventional latches. The modified latch includes a pair of matched output transistors that generate output voltages and a pair of matched biasing circuits to bias the bases of the output transistors with bias voltages. A sample stage is connected so as to apply first biasing currents to one of the biasing circuits in response to input voltages applied to the first latch during the sample period. In addition, a hold stage is connected so as to apply second biasing currents to the biasing circuits during a hold period. The sample and hold stages are configured to apply different voltage differences between the bases of the output transistors.

Abstract: A circuit for generating a digital data signal from an analog input data signal is disclosed. The circuit comprises a master-slave flip-flop with a clock input for receiving the analog input data signal, an amplitude detecting circuit for detecting the amplitude of the analog input data signal and generating an amplitude detection signal in response thereto, and a phase shifting circuit responsive to the amplitude detection signal for supplying a phase shifted signal to the clock input of the master-slave flip-flop. The circuit may further include a clock recovery circuit for generating a recovered clock signal from a clock signal contained in the analog input data signal. The recovered clock signal may be supplied to the amplitude detecting circuit, or a feedback loop may supply the phase shifted clock signal to the amplitude detecting circuit.

Abstract: A logic circuit with improved performance when operating at the limits of the transistor's bandwidth. In particular, a latch includes a clocked trans-admittance stage circuit for receiving a voltage and producing a current output, and an active load, such as a trans-impedance stage circuit, connected to receive as input the current output of the trans-admittance stage circuit and produce a voltage output. Two independent trans-admittance and trans-impedance stages may be combined as a single latch pair. One or more latch pairs may be arranged in series as a cascaded chain and connected to the output current of a clocked trans-admittance stage latch.

Abstract: A logic circuit with improved performance when operating at the limits of the transistor's bandwidth. In particular, a latch includes a clocked trans-admittance stage circuit for receiving a voltage and producing a current output, and an active load, such as a trans-impedance stage circuit, connected to receive as input the current output of the trans-admittance stage circuit and produce a voltage input to the trans-admittance stage. The circuit output is taken from the output of the trans-admittance stage. Two independent trans-admittance and trans-impedance stages may be combined as a single latch pair. One or more latch pairs may be arranged in series as a cascaded chain and connected to the output current of a clocked trans-admittance stage latch to form a register.