Abstract: An embodiment of a process for manufacturing a semiconductor power device envisages the steps of: providing a body made of semiconductor material having a first top surface; forming an active region with a first type of conductivity in the proximity of the first top surface and inside an active portion of the body; and forming an edge-termination structure. The edge-termination structure is formed by: a ring region having the first type of conductivity and a first doping level, set within a peripheral edge portion of the body and electrically connected to the active region; and a guard region, having the first type of conductivity and a second doping level, higher than the first doping level, set in the proximity of the first top surface and connecting the active region to the ring region.

Abstract: An integrated power device includes a semiconductor body of a first conductivity type comprising a first region accommodating a start-up structure, and a second region accommodating a power structure. The two structures are separated from one another by an edge structure and are arranged in a mirror configuration with respect to a symmetry line of the edge structure. Both the start-up structure and the power structure are obtained using MOSFET devices. Both MOSFET devices are multi-drain MOSFET devices, having mesh regions, source regions and gate regions separated from one another. In addition, both MOSFET devices have drain regions delimited by columns that repeat periodically at a fixed distance. Between the two MOSFET devices there is an electrical insulation of at least 25 V.

Abstract: A power electronic device is integrated on a semiconductor substrate of a first type of conductivity. The device includes a plurality of elemental units, and each elemental unit includes a body region of a second type of conductivity which is realized on a semiconductor layer of the first type of conductivity formed on the semiconductor substrate, and a column region of the first type of conductivity which is realized in said semiconductor layer below the body region. The semiconductor layer includes multiple semiconductor layers which overlap each other. The resistivity of each layer is different from that of the other layers. The column region includes a plurality of doped sub-regions, each realized in one of the semiconductor layers. The amount of charge of each doped sub-region balances the amount of charge of the corresponding semiconductor layer in which each doped sub-region is realized.

Abstract: A process realizes a Schottky contact on an epitaxial layer of a semiconductor substrate. The process includes depositing a conductive metallic layer on a surface of the epitaxial layer, with achievement of a interface region of conductive metallic layer/semiconductor. The process further comprises a ionic irradiation step directed towards the surface of the epitaxial layer for forming a modified intermediate layer of at least one surface portion of the epitaxial layer for making the electric behavior of the interface region substantially dependant on the contact between the conductive metallic layer and the obtained modified intermediate layer.

Abstract: An integrated device comprising a MOS transistor and a Schottky diode which are formed on a semiconductor substrate of a first conductivity type is shown. The device comprises a plurality of body region stripes of a second conductivity type which are adjacent and parallel to each other, a first metal layer placed over said substrate and a second metal layer placed under said substrate. The device comprises a plurality of elementary structures parallel to each other each one of which comprises first zones provided with a silicon oxide layer placed over a portion of the substrate which is comprised between two adjacent body region stripes, a polysilicon layer superimposed to the silicon oxide layer, a dielectric layer placed over and around the polysilicon layer. Some body region stripes comprise source regions of the first conductivity type which are placed adjacent to the first zones of the elementary structures to form elementary cells of said MOS transistor.

Abstract: An integrated device comprising a MOS transistor and a Schottky diode which are formed on a semiconductor substrate of a first conductivity type is shown. The device comprises a plurality of body region stripes of a second conductivity type which are adjacent and parallel to each other, a first metal layer placed over said substrate and a second metal layer placed under said substrate. The device comprises a plurality of elementary structures parallel to each other each one of which comprises first zones provided with a silicon oxide layer placed over a portion of the substrate which is comprised between two adjacent body region stripes, a polysilicon layer superimposed to the silicon oxide layer, a dielectric layer placed over and around the polysilicon layer. Some body region stripes comprise source regions of the first conductivity type which are placed adjacent to the first zones of the elementary structures to form elementary cells of said MOS transistor.

Abstract: An integrated device comprising a MOS transistor and a Schottky diode which are formed on a semiconductor substrate of a first conductivity type is shown. The device comprises a plurality of body region stripes of a second conductivity type which are adjacent and parallel to each other, a first metal layer placed over said substrate and a second metal layer placed under said substrate. The device comprises a plurality of elementary structures parallel to each other each one of which comprises first zones provided with a silicon oxide layer placed over a portion of the substrate which is comprised between two adjacent body region stripes, a polysilicon layer superimposed to the silicon oxide layer, a dielectric layer placed over and around the polysilicon layer. Some body region stripes comprise source regions of the first conductivity type which are placed adjacent to the first zones of the elementary structures to form elementary cells of said MOS transistor.

Abstract: A semiconductor device for electro-optic applications includes a rare-earth ions doped P/N junction integrated on a semiconductor substrate. The semiconductor device may be used to obtain laser action in silicon. The rare-earth ions are in a depletion layer of the doped P/N junction, and are for providing a coherent light source cooperating with a waveguide defined by the doped P/N junction. The doped P/N junction may be the base-collector region of a bipolar transistor, and is reverse biased so that the rare-earth ions provide the coherent light.

Abstract: An integrated device comprising a MOS transistor and a Schottky diode which are formed on a semiconductor substrate of a first conductivity type is shown. The device comprises a plurality of body region stripes of a second conductivity type which are adjacent and parallel to each other, a first metal layer placed over said substrate and a second metal layer placed under said substrate. The device comprises a plurality of elementary structures parallel to each other each one of which comprises first zones provided with a silicon oxide layer placed over a portion of the substrate which is comprised between two adjacent body region stripes, a polysilicon layer superimposed to the silicon oxide layer, a dielectric layer placed over and around the polysilicon layer. Some body region stripes comprise source regions of the first conductivity type which are placed adjacent to the first zones of the elementary structures to form elementary cells of said MOS transistor.

Abstract: A method for forming isolating structures in a silicon carbide layer includes depositing a masking layer on first and second portions of the silicon carbide layer, and forming openings through the masking layer to expose the first portions of the silicon carbide layer. Ions are implanted into the first portions of the silicon carbide layer. The silicon carbide layer is heated to form an oxide layer thereon having first portions on the first portions of the silicon carbide layer, and having second portions on the second portions of the silicon carbide layer. The first portions of the oxide layer are etched to form isolating regions in the silicon carbide layer.

Abstract: A method of fabricating electronic devices, integrated monolithically in a semiconductor substrate having at least one non-active area contiguous with at least one device active area, which method comprises at least one step of implanting ions of a noble gas, followed by a thermal treatment to form getter microcavities in the semiconductor by evaporation of the noble gas, wherein the implanting step is carried out in the non-active area of the semiconductor.

Abstract: A method for forming isolating structures in a silicon carbide layer includes depositing a masking layer on first and second portions of the silicon carbide layer, and forming openings through the masking layer to expose the first portions of the silicon carbide layer. Ions are implanted into the first portions of the silicon carbide layer. The silicon carbide layer is heated to form an oxide layer thereon having first portions on the first portions of the silicon carbide layer, and having second portions on the second portions of the silicon carbide layer. The first portions of the oxide layer are etched to form isolating regions in the silicon carbide layer.

Abstract: This invention relates to a method for manufacturing electronic devices integrated monolithically in a semiconductor substrate delimited by two opposed front and back surfaces of a semiconductor material wafer. The method comprises at least a step of implanting ions of a noble gas, followed by a thermal treatment directed to form gettering microvoids in the semiconductor by evaporation of the gas. The ion implanting step is carried out through the back surface of the semiconductor wafer prior to starting the manufacturing process for the electronic devices, and also can be before the step of cleaning the front surface of the wafer.

Abstract: An infrared detector device having a PN junction formed by a first semiconductor material region doped with rare earth ions and by a second semiconductor material region of opposite doping type. The detector device comprises a waveguide formed by a projecting structure extending on a substrate, including a reflecting layer and laterally delimited by a protection and containment oxide region. At least one portion of the waveguide is formed by the PN junction and has an end fed with light to be detected. The detector device has electrodes disposed laterally to and on the waveguide to enable efficient gathering of charge carriers generated by photoconversion.

Abstract: The present invention relates to a Schottky barrier diode which contains a substrate region of a first conductivity type formed in a semiconductor material layer of same conductivity type and a metal layer. A doped region of a second conductive type is formed in the semiconductor layer, with the doped region disposed under the material layer and separated from other doped regions by portions of the semiconductor layer.

Abstract: A MOS technology power device is described which comprises a plurality of elementary active units and a part of said power device which is placed between zones where the elementary active units are formed. The part of the power device comprises at least two heavily doped body regions of a first conductivity type which are formed in a semiconductor layer of a second conductivity type, a first lightly doped semiconductor region of the first conductivity type which is placed laterally between the two body regions. The first semiconductor region is placed under a succession of a thick silicon oxide layer, a polysilicon layer and a metal layer.

Abstract: A MOS technology power device is described which comprises a plurality of elementary active units and a part (1) of said power device which is placed between zones where the elementary active units are formed. The part (1) of the power device comprises at least two heavily doped body regions (4) of a first conductivity type which are formed in a semiconductor layer (3) of a second conductivity type, a first lightly doped semiconductor region (5) of the first conductivity type which is placed laterally between the two body regions (4). The first semiconductor region (5) is placed under a succession of a thick silicon oxide layer (9), a polysilicon layer (10) and a metal layer (13).

Abstract: A method of fabricating electronic devices, integrated monolithically in a semiconductor substrate having at least one non-active area contiguous with at least one device active area, which method comprises at least one step of implanting ions of a noble gas, followed by a thermal treatment to form getter microcavities in the semiconductor by evaporation of the noble gas, wherein the implanting step is carried out in the non-active area of the semiconductor.