Abstract: A central processor of a telecommunication system, operating in a time-division mode, communicates with a peripheral unit through an interface unit including a receiving section and a transmitting section. A control component in the receiving section commands the writing of a signalization messages from the processor in a random-access memory, in cells addressed by counting signals from the peripheral unit in respective time slots of a scanning cycle. The stored signalization messages are read out, in the first half of a time slot immediately preceding the one in which they are to be utilized in the peripheral unit, for relaying to that unit; the second half of each time slot serves for the writing of new messages in the memory or for the deletion of previously stored messages in response to cancellation signals from the peripheral unit, all with the aid of instructions extracted from a microprogram store in the control component of the receiving section.