Patents by Inventor Mario Torre
Mario Torre has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240093808Abstract: A system for spacing and fastening tubular structures, and a related method. The system includes a spacer element configured to engage a plurality of tubular structures, to spatially separate the plurality of tubular structures from one another, and to distribute stress in the plurality of tubular structures. The system further includes a fastening element configured to extend around at least a portion of an outer surface of the plurality of tubular structures, and to fasten the plurality of tubular structures to the spacer element in an adaptively spaced configuration.Type: ApplicationFiled: December 1, 2023Publication date: March 21, 2024Inventors: Naleen Kumar Verma, Mario Alberto Bolaños Jimenez, Arun Ramachandra, Jeffrey P. Darnell, Michael E. Sandy, José Torre
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Patent number: 11764257Abstract: A disclosed super-junction (SJ) device includes a first epitaxial (epi) layer that forms a first SJ layer of the SJ device, and includes a second epi layer disposed on the first SJ layer that forms a device layer of the SJ device. An active area of the first and second epi layers includes a first set of SJ pillars comprising a particular doping concentration of a first conductivity type and a second set of SJ pillars comprising the particular doping concentration of a second conductivity type. A termination area of the first and second epi layers has a minimized epi doping concentration of the first conductivity type that is less than the particular doping concentration, and the termination area of the second epi layer includes a plurality of floating regions of the second conductivity type that form a junction termination of the SJ device.Type: GrantFiled: January 10, 2022Date of Patent: September 19, 2023Assignee: General Electric CompanyInventors: Stephen Daley Arthur, Victor Mario Torres, Michael J. Hartig, Reza Ghandi, David Alan Lilienfeld, Alexander Viktorovich Bolotnikov
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Publication number: 20220130953Abstract: A disclosed super-junction (SJ) device includes a first epitaxial (epi) layer that forms a first SJ layer of the SJ device, and includes a second epi layer disposed on the first SJ layer that forms a device layer of the SJ device. An active area of the first and second epi layers includes a first set of SJ pillars comprising a particular doping concentration of a first conductivity type and a second set of SJ pillars comprising the particular doping concentration of a second conductivity type. A termination area of the first and second epi layers has a minimized epi doping concentration of the first conductivity type that is less than the particular doping concentration, and the termination area of the second epi layer includes a plurality of floating regions of the second conductivity type that form a junction termination of the SJ device.Type: ApplicationFiled: January 10, 2022Publication date: April 28, 2022Inventors: Stephen Daley Arthur, Victor Mario Torres, Michael J. Hartig, Reza Ghandi, David Alan Lilienfeld, Alexander Viktorovich Bolotnikov
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Patent number: 11271076Abstract: The subject matter disclosed herein relates to semiconductor power devices and, more specifically, to junction termination designs for wide-bandgap (e.g., silicon carbide) semiconductor power devices. A disclosed semiconductor device includes a first epitaxial (epi) layer disposed on a substrate layer, wherein a termination area of the first epi layer has a minimized epi doping concentration of a first conductivity type (e.g., n-type). The device also includes a second epi layer disposed on the first epi layer, wherein a termination area of the second epi layer has the minimized epi doping concentration of the first conductivity type and includes a first plurality of floating regions of a second conductivity type (e.g., p-type) that form a first junction termination of the device.Type: GrantFiled: July 19, 2019Date of Patent: March 8, 2022Assignee: GENERAL ELECTRIC COMPANYInventors: Stephen Daley Arthur, Victor Mario Torres, Michael J. Hartig, Reza Ghandi, David Alan Lilienfeld, Alexander Viktorovich Bolotnikov
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Patent number: 11245003Abstract: A disclosed super-junction (SJ) device includes a first epitaxial (epi) layer that forms a first SJ layer of the SJ device, and includes a second epi layer disposed on the first SJ layer that forms a device layer of the SJ device. An active area of the first and second epi layers includes a first set of SJ pillars comprising a particular doping concentration of a first conductivity type and a second set of SJ pillars comprising the particular doping concentration of a second conductivity type. A termination area of the first and second epi layers has a minimized epi doping concentration of the first conductivity type that is less than the particular doping concentration, and the termination area of the second epi layer includes a plurality of floating regions of the second conductivity type that form a junction termination of the SJ device.Type: GrantFiled: July 19, 2019Date of Patent: February 8, 2022Assignee: GENERAL ELECTRIC COMPANYInventors: Stephen Daley Arthur, Victor Mario Torres, Michael J. Hartig, Reza Ghandi, David Alan Lilienfeld, Alexander Viktorovich Bolotnikov
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Patent number: 10969409Abstract: Miniaturized current sensors are disclosed herein. The miniaturized current sensors may employ a coiled coil and a return coil around the current path to be measured. The miniaturized current sensors may be integrated to microelectronic devices and components.Type: GrantFiled: December 28, 2018Date of Patent: April 6, 2021Assignee: General Electric CompanyInventor: Victor Mario Torres
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Patent number: 10741551Abstract: An integrated circuit die that may have one vertical transistor and one horizontal transistor is disclosed. The transistors may have substantially different breakdown voltages. The vertical transistor may be used in power circuitry applications and the horizontal transistor may be used in logic circuitry applications.Type: GrantFiled: December 28, 2018Date of Patent: August 11, 2020Assignee: GENERAL ELECTRIC COMPANYInventor: Victor Mario Torres
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Publication number: 20200209284Abstract: Miniaturized current sensors are disclosed herein. The miniaturized current sensors may employ a coiled coil and a return coil around the current path to be measured. The miniaturized current sensors may be integrated to microelectronic devices and components.Type: ApplicationFiled: December 28, 2018Publication date: July 2, 2020Inventor: Victor Mario Torres
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Publication number: 20200212034Abstract: An integrated circuit die that may have one vertical transistor and one horizontal transistor is disclosed. The transistors may have substantially different breakdown voltages. The vertical transistor may be used in power circuitry applications and the horizontal transistor may be used in logic circuitry applications.Type: ApplicationFiled: December 28, 2018Publication date: July 2, 2020Inventor: Victor Mario Torres
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Publication number: 20200203476Abstract: The subject matter disclosed herein relates to semiconductor power devices and, more specifically, to junction termination designs for wide-bandgap (e.g., silicon carbide) semiconductor power devices. A disclosed semiconductor device includes a first epitaxial (epi) layer disposed on a substrate layer, wherein a termination area of the first epi layer has a minimized epi doping concentration of a first conductivity type (e.g., n-type). The device also includes a second epi layer disposed on the first epi layer, wherein a termination area of the second epi layer has the minimized epi doping concentration of the first conductivity type and includes a first plurality of floating regions of a second conductivity type (e.g., p-type) that form a first junction termination of the device.Type: ApplicationFiled: July 19, 2019Publication date: June 25, 2020Inventors: Stephen Daley Arthur, Victor Mario Torres, Michael J. Hartig, Reza Ghandi, David Alan Lilienfeld, Alexander Viktorovich Bolotnikov
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Publication number: 20200203477Abstract: A disclosed super-junction (SJ) device includes a first epitaxial (epi) layer that forms a first SJ layer of the SJ device, and includes a second epi layer disposed on the first SJ layer that forms a device layer of the SJ device. An active area of the first and second epi layers includes a first set of SJ pillars comprising a particular doping concentration of a first conductivity type and a second set of SJ pillars comprising the particular doping concentration of a second conductivity type. A termination area of the first and second epi layers has a minimized epi doping concentration of the first conductivity type that is less than the particular doping concentration, and the termination area of the second epi layer includes a plurality of floating regions of the second conductivity type that form a junction termination of the SJ device.Type: ApplicationFiled: July 19, 2019Publication date: June 25, 2020Inventors: Stephen Daley Arthur, Victor Mario Torres, Michael J. Hartig, Reza Ghandi, David Alan Lilienfeld, Alexander Viktorovich Bolotnikov
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Publication number: 20180190791Abstract: The present disclosure relates to a symmetrical, punch-through transient voltage suppression (TVS) device includes a mesa structure disposed on a semiconductor substrate. The mesa structure includes a first semiconductor layer of a first conductivity-type, a second semiconductor layer of a second conductivity-type disposed on the first semiconductor layer, and a third semiconductor layer of the first conductive-type disposed on the second semiconductor layer. The mesa structure also includes beveled sidewalls forming mesa angles with respect to the semiconductor substrate and edge implants disposed at lateral edges of the second semiconductor layer. The edge implants including dopants of the second conductive-type are configured to cause punch-through to occur in a bulk region and not in the lateral edges of the second semiconductor layer.Type: ApplicationFiled: January 4, 2017Publication date: July 5, 2018Inventors: Victor Mario Torres, Reza Ghandi, David Alan Lilienfeld, Avinash Srikrishnan Kashyap, Alexander Viktorovich Bolotnikov
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Patent number: 10014388Abstract: The present disclosure relates to a symmetrical, punch-through transient voltage suppression (TVS) device includes a mesa structure disposed on a semiconductor substrate. The mesa structure includes a first semiconductor layer of a first conductivity-type, a second semiconductor layer of a second conductivity-type disposed on the first semiconductor layer, and a third semiconductor layer of the first conductive-type disposed on the second semiconductor layer. The mesa structure also includes beveled sidewalls forming mesa angles with respect to the semiconductor substrate and edge implants disposed at lateral edges of the second semiconductor layer. The edge implants including dopants of the second conductive-type are configured to cause punch-through to occur in a bulk region and not in the lateral edges of the second semiconductor layer.Type: GrantFiled: January 4, 2017Date of Patent: July 3, 2018Assignee: GENERAL ELECTRIC COMPANYInventors: Victor Mario Torres, Reza Ghandi, David Alan Lilienfeld, Avinash Srikrishnan Kashyap, Alexander Viktorovich Bolotnikov
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Publication number: 20180176104Abstract: Implementations of the present disclosure provide for generating adjacency graph from a series of linear linked data structures. A method of one implementation includes receiving an input of a series of linear linked data structures (links). Each of the plurality of links includes an element among a plurality of elements. The method includes in response to determining that a first instance of a node among a plurality of nodes corresponding to an element among the plurality of elements does not exist in the tree graph, generating the first instance of the node in the tree graph. The method also includes creating an edge directly from a second node to the generated first instance of the node. The second node corresponds to a second element among the plurality of elements that is directly linked to the element. The method further generating an adjacency graph based on traversing of the tree graph.Type: ApplicationFiled: December 15, 2016Publication date: June 21, 2018Inventors: Mario Torre, Andrew Dinn
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Patent number: 10003510Abstract: Implementations of the present disclosure provide for generating adjacency graph from a series of linear linked data structures. A method of one implementation includes receiving an input of a series of linear linked data structures (links). Each of the plurality of links includes an element among a plurality of elements. The method includes in response to determining that a first instance of a node among a plurality of nodes corresponding to an element among the plurality of elements does not exist in the tree graph, generating the first instance of the node in the tree graph. The method also includes creating an edge directly from a second node to the generated first instance of the node. The second node corresponds to a second element among the plurality of elements that is directly linked to the element. The method further generating an adjacency graph based on traversing of the tree graph.Type: GrantFiled: December 15, 2016Date of Patent: June 19, 2018Assignee: Red Hat, Inc.Inventors: Mario Torre, Andrew Dinn
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Publication number: 20180073675Abstract: A piñata holding device for holding a piñata may include a first support arm being substantially vertical and being rotatably connected to a support surface; and a second pivot arm to pivot with respect to the first support arm; and a third support arm connected to the second pivot arm to extend and hold the piñata.Type: ApplicationFiled: December 16, 2016Publication date: March 15, 2018Inventor: Angel Mario Torres
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Publication number: 20180056412Abstract: A device for mounting a circular saw may include a support base to support device and the circular saw; a detachably connected spacer device to provide variable cuts for the circular saw; a spacer arm to connect to the support base; and a traverse rail to connect to the spacer arm and to connect to the circular saw.Type: ApplicationFiled: October 16, 2016Publication date: March 1, 2018Inventor: Angel Mario Torres
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Patent number: 9861511Abstract: The present invention relates to a drainage bag support apparatus that has a trunk belt, one or more support straps, and additional means to connect the trunk belt and the support straps together, to adjust the support strap, and to attach a drainage bag. The apparatus of the present invention allows one to adjust and lock the length of the support strap, to change the positions of the trunk belt and the support straps, and to use one or more drainage bags. Methods of using the drainage bag support apparatus include securing the trunk belt around an individual and securing one or more drainage bags to the drainage bag support apparatus. Kits that provide the components of the drainage bag support apparatus to be used along with at least one drainage bag are also described herein.Type: GrantFiled: January 8, 2014Date of Patent: January 9, 2018Inventor: Mario Torres-Leon
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Publication number: 20140196792Abstract: The present invention relates to a three-way valve case that has a top member, bottom member, closure member, three openings, and a hinge allowing the case to be opened and closed. The case may be adapted to receive a three-way valve. Apart from a case adapted to receive a three-way valve, a three-way valve case apparatus is also disclosed. The apparatus includes a three-way valve having three ports, a base, and an operator; and a case having a top member, bottom member, hinge, openings to receive the ports of the valve, and a closure member to support the closed state of the case.Type: ApplicationFiled: January 17, 2014Publication date: July 17, 2014Applicant: Global Medical Innovations, LLCInventor: Mario Torres-Leon
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Publication number: 20140194839Abstract: The present invention relates to a drainage bag support apparatus that has a trunk belt, one or more support straps, and additional means to connect the trunk belt and the support straps together, to adjust the support strap, and to attach a drainage bag. The apparatus of the present invention allows one to adjust and lock the length of the support strap, to change the positions of the trunk belt and the support straps, and to use one or more drainage bags. Methods of using the drainage bag support apparatus include securing the trunk belt around an individual and securing one or more drainage bags to the drainage bag support apparatus. Kits that provide the components of the drainage bag support apparatus to be used along with at least one drainage bag are also described herein.Type: ApplicationFiled: January 8, 2014Publication date: July 10, 2014Applicant: GLOBAL MEDICAL INNOVATIONS, LLCInventor: Mario Torres-Leon