Abstract: Examples include a method of identifying single twisted pair cable Ethernet auto-negotiation requests or double twisted pair cables Ethernet auto-negotiation requests using detection of message time interval patterns. The method includes receiving, by a first Ethernet device, a plurality of messages transmitted by a second Ethernet device over a single twisted pair cable connecting the first Ethernet device and the second Ethernet device; storing one or more time intervals between starting times of successive pairs of the plurality of messages; determining if a pattern is found in the time intervals; when the pattern is found, setting a single twisted pair cable communications mode between the first Ethernet device and the second Ethernet device; and performing priority resolution between the first Ethernet device and the second Ethernet device.

Abstract: A device comprises a clock source configured to provide a spread-spectrum modulated clock signal and a control signal associated with the spread-spectrum modulated clock signal. The device also comprises a circuitry configured to receive the spread-spectrum modulated clock signal, to receive the control signal, and to sample a data signal in accordance with the spread-spectrum modulated clock signal and the control signal.

Abstract: Examples include a method of identifying single twisted pair cable Ethernet auto-negotiation requests or double twisted pair cables Ethernet auto-negotiation requests using detection of message time interval patterns. The method includes receiving, by a first Ethernet device, a plurality of messages transmitted by a second Ethernet device over a single twisted pair cable connecting the first Ethernet device and the second Ethernet device; storing one or more time intervals between starting times of successive pairs of the plurality of messages; determining if a pattern is found in the time intervals; when the pattern is found, setting a single twisted pair cable communications mode between the first Ethernet device and the second Ethernet device; and performing priority resolution between the first Ethernet device and the second Ethernet device.

Abstract: A method and apparatus for preventing inherent error propagation of a successive approximation register (SAR)-based analog-to-digital converter (ADC) through digital correction. A sample-and-hold circuit captures an input analog signal and generates a hold sample of the input analog signal. A digital-to-analog converter (DAC) generates an iterative sample corresponding to a digital code for each iteration. A comparator compares the hold sample and the iterative sample and generates a decision signal based on the comparison. A successive approximation register updates the digital code for each iteration based on the decision signal and supplies the updated digital code to the DAC. The SAR ADC includes an error detection circuit to detect an error condition. A controller ceases iteration operation if the error condition is detected and outputs the current digital code as a result.

Abstract: According to one embodiment, an Ethernet communication device is configured to be connected to one or more twisted-pair links, each twisted-pair link having a particular capacity. The Ethernet communication device includes a physical interface transceiver. The physical interface transceiver sets a data transmission rate of the Ethernet communication device based on a total capacity of the twisted-pair links connected to the Ethernet communication device. The physical interface transceiver transmits data over the twisted-pair links connected to the Ethernet communication device at the data transmission rate.

Abstract: A device comprises a clock source configured to provide a spread-spectrum modulated clock signal and a control signal associated with the spread-spectrum modulated clock signal. The device also comprises a circuitry configured to receive the spread-spectrum modulated clock signal, to receive the control signal, and to sample a data signal in accordance with the spread-spectrum modulated clock signal and the control signal.

Abstract: A method and apparatus for preventing inherent error propagation of a successive approximation register (SAR)-based analog-to-digital converter (ADC) through digital correction. A sample-and-hold circuit captures an input analog signal and generates a hold sample of the input analog signal. A digital-to-analog converter (DAC) generates an iterative sample corresponding to a digital code for each iteration. A comparator compares the hold sample and the iterative sample and generates a decision signal based on the comparison. A successive approximation register updates the digital code for each iteration based on the decision signal and supplies the updated digital code to the DAC. The SAR ADC includes an error detection circuit to detect an error condition. A controller ceases iteration operation if the error condition is detected and outputs the current digital code as a result.

Abstract: A method and a corresponding device for providing a delay value of a communication electronic unit. A digital input signal is delayed by a delay element. The input and the output signals of the delay element are sampled and the sampled signals are compared. A mismatch counter is incremented when the amplitudes of the sampled signals are not equal and a signal transition counter N is incremented when the input signal transitions. The provided delay value is proportional to the mismatch counting value, proportional to the length of the sampling intervals and inversely proportional to the signal transition counting value.

Abstract: A method and a corresponding device for providing a delay value of a communication electronic unit. A digital input signal is delayed by a delay element. The input and the output signals of the delay element are sampled and the sampled signals are compared. A mismatch counter is incremented when the amplitudes of the sampled signals are not equal and a signal transition counter N is incremented when the input signal transitions. The provided delay value is proportional to the mismatch counting value, proportional to the length of the sampling intervals and inversely proportional to the signal transition counting value.

Abstract: According to one embodiment, an Ethernet physical interface transceiver comprises a link interface configured to be segmented into one or more active ports. First circuitry is configured to transmit and receive data either at a relatively high data rate via a single active port of the link interface when the transceiver is configured in a first mode or at a relatively low data rate via at least two different active ports of the link interface when the transceiver is configured in a second mode. Second circuitry is configured to communicate with a media access controller either at a relatively high data rate when the transceiver is configured in the first mode or at a relatively low data rate when the transceiver is configured in the second mode. Clock circuitry is configured to independently synchronize operation of each active port of the link interface.

Abstract: Embodiments related to noise compensation in data transmission are described and depicted.

Abstract: According to one embodiment, an Ethernet physical interface transceiver comprises a link interface configured to be segmented into one or more active ports. First circuitry is configured to transmit and receive data either at a relatively high data rate via a single active port of the link interface when the transceiver is configured in a first mode or at a relatively low data rate via at least two different active ports of the link interface when the transceiver is configured in a second mode. Second circuitry is configured to communicate with a media access controller either at a relatively high data rate when the transceiver is configured in the first mode or at a relatively low data rate when the transceiver is configured in the second mode. Clock circuitry is configured to independently synchronize operation of each active port of the link interface.

Abstract: According to one embodiment, an Ethernet communication device is configured to be connected to one or more twisted-pair links, each twisted-pair link having a particular capacity. The Ethernet communication device includes a physical interface transceiver. The physical interface transceiver sets a data transmission rate of the Ethernet communication device based on a total capacity of the twisted-pair links connected to the Ethernet communication device. The physical interface transceiver transmits data over the twisted-pair links connected to the Ethernet communication device at the data transmission rate.

Abstract: An integrated circuit comprises an output terminal to be coupled to a non-linear circuit element, an output circuit coupled to the output terminal, the output circuit being configured to supply an operating signal to the non-linear circuit element, a measuring circuit coupled to the output terminal, the measuring circuit being configured to sense on the output terminal a signal value outside an operating regime of the non-linear circuit element, and a control circuit coupled to the measuring circuit, the control circuit being configured to configure at least one function of the integrated circuit on the basis of the signal value sensed by the measuring circuit.

Abstract: A device is provided for measuring properties of transmission links by an adaptive filter. The device comprises a first output terminal adapted to provide a first signal to the transmission link. Further, the device includes a first input terminal for receiving an echo signal of the first signal. An adaptive filter forms a part of the device and is coupled to the first input terminal. The device includes a second output terminal for providing information identifying filter coefficient of the adaptive filter.

Abstract: Viterbi decoder for decoding a received sequence of data symbols which are coded using a predetermined coding instruction is provided. The Viterbi decoder includes a branch metric calculation circuit for calculation of branch metrics for the received sequence of coded data symbols. The Viterbi decoder includes a path metric calculation circuit for calculation of path metrics as a function of the branch metrics and the coding instruction, with the calculated path metrics in each case being compared with an adjustable decision threshold value in order to produce an associated logic validity value. The Viterbi decoder also includes a selection circuit which temporarily stores those path metrics whose validity value is logic high in a memory, and selects from the temporarily stored path metrics that path with the optimum path metric.

Abstract: For a Virerbi decoder, it is proposed to combine the butterfly structures of the corresponding trellis diagram in pairs in such a way that for each butterfly structure pair, the destination states of the two butterfly structures in the trellis diagram at the same time form starting states for two other butterfly structures. After the determination of the path metrics of the destination states one of the two butterfly structures of a butterfly structure pair, in each case the path metrics of those two destination states of this butterfly structure pair which at the same time form starting states of another butterfly structure are then stored in the form of a common memory word.

Abstract: An ACS unit is proposed for a Viterbi decoder, which, in order to determine the path metrics of two states of a time step in a trellis diagram, compares the difference (&Ggr;) between the path metrics of the two states (19, 20) which are linked via branches to these two states in the form of a butterfly structure, of the preceding time step in the trellis diagram, with the difference (&Lgr;) between the corresponding branch metrics. The structure of the ACS unit is simplified in that the mathematical signals (sg(&Ggr;), sg(&Lgr;)) of the two differences are also evaluated.

Abstract: Viterbi decoder for decoding a received sequence of data symbols which are coded using a predetermined coding instruction, having:

Abstract: For a Viterbi decoder, it is proposed to combine the butterfly structures of the corresponding trellis diagram in pairs in such a way that for each butterfly structure pair, the destination states of the two butterfly structures in the trellis diagram at the same time form starting states for two other butterfly structures. After the determination of the path metrics of the destination states of the two butterfly structures of a butterfly structure pair, in each case the path metrics of those two destination states of this butterfly structure pair which are the same time form starting states of another butterfly structure are then stored in the form of a common memory word.