Patents by Inventor Mario Velez

Mario Velez has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11412757
    Abstract: The present disclosure provides an improved system and method that includes a food dispensing machine for dispensing a base food product through a dispensing valve and adding ingredients and other additives, such as flavors and the like, to the base food product when the product is dispensed from a product chamber. Apparatuses and methods for maintaining a consistent mix of the base product in the freezing chamber are disclosed as are processes for calibrating desired proportions of ingredients.
    Type: Grant
    Filed: June 27, 2018
    Date of Patent: August 16, 2022
    Assignee: FBD Partnership, LP
    Inventors: Mario A Velez, Edward G Alvarado, Alejandro Z Ramirez, Daniel J Seiler, David Renaud
  • Patent number: 10523253
    Abstract: In an illustrative example, an apparatus includes a passive-on-glass (POG) device integrated within a glass substrate. The apparatus further includes a semiconductor die integrated within the glass substrate.
    Type: Grant
    Filed: July 6, 2018
    Date of Patent: December 31, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Changhan Yun, Chengjie Zuo, Mario Velez, Niranjan Sunil Mudakatte, Shiqun Gu, Jonghae Kim, David Berdy
  • Publication number: 20190373913
    Abstract: The present disclosure provides an improved system and method that includes a food dispensing machine for dispensing a base food product through a dispensing valve and adding ingredients and other additives, such as flavors and the like, to the base food product when the product is dispensed from a product chamber. Apparatuses and methods for maintaining a consistent mix of the base product in the freezing chamber are disclosed as are processes for calibrating desired proportions of ingredients.
    Type: Application
    Filed: June 27, 2018
    Publication date: December 12, 2019
    Applicant: FBD PARTNERSHIP, LP
    Inventors: MARIO A. VELEZ, EDWARD G. ALVARADO, ALEJANDRO Z. RAMIREZ, DANIEL J. SEILER, DAVID RENAUD
  • Patent number: 10325855
    Abstract: A device and method of fabricating are provided. The device includes a substrate having a first side and an opposite second side, a cavity defined within the substrate from the first side, a die coupled to a floor of the cavity and having a conductive pad on a side of the die distal to the floor of the cavity. A laminate layer coupled to the second side of the substrate may be included. A hole may be drilled, at one time, through layers of the device, through the die, and through the conductive pad. The hole extends through and is defined within the laminate layer (if present), the second side of the substrate, the die, and the conductive pad. A conductive material is provided within the hole and extends between and through the laminate layer (if provided), the second side of the substrate, the die, and the conductive pad.
    Type: Grant
    Filed: March 18, 2016
    Date of Patent: June 18, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Daeik Kim, Jie Fu, Changhan Yun, Chin-Kwan Kim, Manuel Aldrete, Chengjie Zuo, Mario Velez, Jonghae Kim
  • Patent number: 10171112
    Abstract: An RF diplexer is provided that includes a first channel and a second channel. The first channel includes a first primary inductor. Similarly, the second channel includes a second primary inductor. A first directional coupler for the first channel includes a first transformer formed by the first primary inductor and also a first secondary inductor. A first terminal for the first secondary inductor is a coupled port for the first directional coupler. A second directional coupler for the second channel includes a second transformer formed by the second primary inductor and also a second secondary inductor. A first terminal for the second secondary inductor is a coupled port for the second directional coupler.
    Type: Grant
    Filed: March 24, 2016
    Date of Patent: January 1, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Yunfei Ma, Chengjie Zuo, David Berdy, Daeik Kim, Changhan Yun, Je-Hsiung Lan, Mario Velez, Niranjan Sunil Mudakatte, Robert Mikulka, Jonghae Kim
  • Publication number: 20180316374
    Abstract: In an illustrative example, an apparatus includes a passive-on-glass (POG) device integrated within a glass substrate. The apparatus further includes a semiconductor die integrated within the glass substrate.
    Type: Application
    Filed: July 6, 2018
    Publication date: November 1, 2018
    Inventors: Changhan Yun, Chengjie Zuo, Mario Velez, Niranjan Sunil Mudakatte, Shiqun Gu, Jonghae Kim, David Berdy
  • Patent number: 10044390
    Abstract: In an illustrative example, an apparatus includes a passive-on-glass (POG) device integrated within a glass substrate. The apparatus further includes a semiconductor die integrated within the glass substrate.
    Type: Grant
    Filed: July 21, 2016
    Date of Patent: August 7, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: Changhan Yun, Chengjie Zuo, Mario Velez, Niranjan Sunil Mudakatte, Shiqun Gu, Jonghae Kim, David Berdy
  • Patent number: 10038422
    Abstract: A single-die multi-FBAR (film bulk acoustic resonator) device includes multiple FBARs having different resonant frequencies formed over a single substrate. The FBARs include piezoelectric layers having different thicknesses but with upper electrodes formed at a same height over the substrate, lower electrodes at different heights over the substrate, and different sized air gaps separating the lower electrodes from the substrate.
    Type: Grant
    Filed: August 25, 2016
    Date of Patent: July 31, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: Changhan Hobie Yun, Je-Hsiung Lan, Chengjie Zuo, David Berdy, Jonghae Kim, Mario Velez, Niranjan Sunil Mudakatte, Shiqun Gu
  • Publication number: 20180061775
    Abstract: A device that includes a single substrate layer, a plurality of interconnects over the single substrate layer, the plurality of interconnects configured to operate as at least one passive component, a first die coupled to the single substrate layer and the plurality of interconnects, and an encapsulation layer that at least partially encapsulates the first die and the plurality of interconnects configured to operate as at least one passive component. In some implementations, the single substrate layer, the first die and the encapsulation layer comprise an overall thickness of about 225 microns (?m) or less. In some implementations, the single substrate layer comprises a thickness of about 75 microns (?m) or less.
    Type: Application
    Filed: August 31, 2016
    Publication date: March 1, 2018
    Inventors: Mario Velez, Niranjan Sunil Mudakatte, Changhan Yun, David Berdy, Shiqun Gu, Jonghae Kim, Chengjie Zuo
  • Publication number: 20180062617
    Abstract: A single-die multi-FBAR (film bulk acoustic resonator) device includes multiple FBARs having different resonant frequencies formed over a single substrate. The FBARs include piezoelectric layers having different thicknesses but with upper electrodes formed at a same height over the substrate, lower electrodes at different heights over the substrate, and different sized air gaps separating the lower electrodes from the substrate.
    Type: Application
    Filed: August 25, 2016
    Publication date: March 1, 2018
    Inventors: Changhan Hobie Yun, Je-Hsiung Lan, Chengjie Zuo, David Berdy, Jonghae Kim, Mario Velez, Niranjan Sunil Mudakatte, Shiqun Gu
  • Publication number: 20180026666
    Abstract: In an illustrative example, an apparatus includes a passive-on-glass (POG) device integrated within a glass substrate. The apparatus further includes a semiconductor die integrated within the glass substrate.
    Type: Application
    Filed: July 21, 2016
    Publication date: January 25, 2018
    Inventors: Changhan Yun, Chengjie Zuo, Mario Velez, Niranjan Sunil Mudakatte, Shiqun Gu, Jonghae Kim, David Berdy
  • Publication number: 20170365570
    Abstract: Some implementations provide a device that includes a passive component and a substrate coupled to the passive component, where a surface of the substrate comprises a first irradiated portion. In some implementations, the first irradiated portion is located in an offset portion of the substrate. Some implementations provide an integrated device that includes a device layer and a substrate coupled to the device layer, where a surface of the substrate comprises a first irradiated portion. In some implementations, the first irradiated portion is located in an offset portion of the substrate.
    Type: Application
    Filed: June 16, 2016
    Publication date: December 21, 2017
    Inventors: Daeik Kim, Chengjie Zuo, Mario Velez, Changhan Yun, Jonghae Kim
  • Publication number: 20170338255
    Abstract: The present disclosure provides integrated circuit apparatuses and methods for manufacturing integrated circuit apparatuses. An integrated circuit apparatus may include a first insulator, the first insulator being substantially planar and having a first top surface and a first bottom surface opposite the first top surface, a first conductor disposed on the first insulator, a second insulator, the second insulator being substantially planar and having a second top surface and a second bottom surface opposite the second top surface, a second conductor disposed on the second insulator, and a dielectric layer disposed between the first bottom conductor of the first insulator and the second top conductor of the second insulator.
    Type: Application
    Filed: May 20, 2016
    Publication date: November 23, 2017
    Inventors: Changhan Hobie YUN, Daeik Daniel KIM, Jonghae KIM, Mario Mario VELEZ, Chengjie ZUO, David Francis BERDY
  • Publication number: 20170279469
    Abstract: An RF diplexer is provided with an integrated diplexer that shares a primary inductor included in a channel within the RF diplexer.
    Type: Application
    Filed: March 24, 2016
    Publication date: September 28, 2017
    Inventors: Yunfei Ma, Chengjie Zuo, David Berdy, Daeik Kim, Changhan Yun, Je-Hsiung Lan, Mario Velez, Niranjan Sunil Mudakatte, Robert Mikulka, Jonghae Kim
  • Publication number: 20170271266
    Abstract: A device and method of fabricating are provided. The device includes a substrate having a first side and an opposite second side, a cavity defined within the substrate from the first side, a die coupled to a floor of the cavity and having a conductive pad on a side of the die distal to the floor of the cavity. A laminate layer coupled to the second side of the substrate may be included. A hole may be drilled, at one time, through layers of the device, through the die, and through the conductive pad. The hole extends through and is defined within the laminate layer (if present), the second side of the substrate, the die, and the conductive pad. A conductive material is provided within the hole and extends between and through the laminate layer (if provided), the second side of the substrate, the die, and the conductive pad.
    Type: Application
    Filed: March 18, 2016
    Publication date: September 21, 2017
    Inventors: Daeik Kim, Jie Fu, Changhan Yun, Chin-Kwan Kim, Manuel Aldrete, Chengjie Zuo, Mario Velez, Jonghae Kim
  • Publication number: 20070096268
    Abstract: The disclosure provides integrated circuit packages including a lead frame having multiple I/O pads positioned proximate to the lead frame perimeter around a central ground paddle, an integrated circuit die having electrically conductive die terminals positioned on the central ground paddle, and multiple ground circuit pads positioned on and in electrical connection with the central ground paddle. Electrically conductive I/O circuit pads are arranged about the die between the ground circuit pads and the I/O pads, each I/O circuit pad electrically connected to one of the I/O pads. Electrically conductive bond wires connect one or more of the die terminals to one or more I/O circuit pads or one or more ground circuit pads. In certain embodiments, the disclosure further provides an integrated circuit positioned to engage the integrated circuit die in electrical connection with the die terminals. The disclosure also relates to methods of packaging an integrated circuit to reduce packaging parasitics.
    Type: Application
    Filed: April 5, 2006
    Publication date: May 3, 2007
    Inventors: Laxminarayan Sharma, Mario Velez