Patents by Inventor Mario Vigliar

Mario Vigliar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Hardware coprocessor for stripe-based interest point detection
    Patent number: 9020276
    Abstract: A hardware coprocessor architecture calculates the Difference-of-Gaussian (DoG) pyramid of an input image and extracts from this the interest points to be used in several image detection algorithms. Advantages of the architecture include the possibility to process the image by stripes, namely by blocks having one dimension coincident with the input image width, in the absence of an input frame buffer and the possibility to avoid RAM memory. The coprocessor is suitable to be tightly coupled with raw image sources like sensors.
    Type: Grant
    Filed: April 24, 2013
    Date of Patent: April 28, 2015
    Assignee: STMicroelectronics S.r.l.
    Inventors: Mario Vigliar, Gian Domenico Licciardo
  • Multiplierless coprocessor for difference of Gaussian (DoG) calculation
    Patent number: 9014508
    Abstract: A hardware architecture is applied to the calculation of a Difference-of-Gaussian filter, which is typically employed in image processing algorithms. The architecture has a modular structure to easily allow the matching of the desired delay/area ratio as well as a high computational accuracy. A new solution is provided for the implementation of multiply-accumulators which allows a significant reduction of area with respect to the conventional architectures.
    Type: Grant
    Filed: April 24, 2013
    Date of Patent: April 21, 2015
    Assignee: STMicroelectronics S.r.l.
    Inventors: Mario Vigliar, Gian Domenico Licciardo
  • MULTIPLIERLESS COPROCESSOR FOR DIFFERENCE OF GAUSSIAN (DOG) CALCULATION
    Publication number: 20130301950
    Abstract: A hardware architecture is applied to the calculation of a Difference-of-Gaussian filter, which is typically employed in image processing algorithms. The architecture has a modular structure to easily allow the matching of the desired delay/area ratio as well as a high computational accuracy. A new solution is provided for the implementation of multiply-accumulators which allows a significant reduction of area with respect to the conventional architectures.
    Type: Application
    Filed: April 24, 2013
    Publication date: November 14, 2013
    Inventors: Mario Vigliar, Gian Domenico Licciardo