Patents by Inventor Marios Barlas
Marios Barlas has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11944022Abstract: A resistive memory cell may be provided with a first electrode and a second electrode arranged on either side of a dielectric layer and facing an interface between a first region and a second region, The first and second region may have different compositions in terms of doping and/or dielectric constant, so as to confine the zone of reversible creation of a conductive filament at the interface.Type: GrantFiled: August 30, 2021Date of Patent: March 26, 2024Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVESInventors: Laurent Grenouillet, Marios Barlas, Etienne Nowak
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Publication number: 20230335566Abstract: The present description concerns a manufacturing method comprising, for each photodetector of an array of photodetectors of a light sensor, a use of a mask obtained by directed self-assembly of a block copolymer to form, by a first etch step, at least one first structure on the side of a first surface of the photodetector intended to receive light.Type: ApplicationFiled: February 27, 2023Publication date: October 19, 2023Applicants: STMicroelectronics (Crolles 2) SAS, COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVESInventors: Marios BARLAS, Quentin ABADIE
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Publication number: 20230290813Abstract: A device includes at least one capacitor. The capacitor includes an assembly of two metal pads and at least two metal plates, each plate extending at least from one pad to the other, a first insulating layer conformally covering said assembly, a second conductive layer conformally covering the first layer.Type: ApplicationFiled: March 3, 2023Publication date: September 14, 2023Applicant: STMicroelectronics (Crolles 2) SASInventor: Marios BARLAS
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Publication number: 20230290570Abstract: A device includes a first layer, having a copper track located therein. The first layer is covered with a second layer including a cavity. The cavity exposes at least a portion of the track. The portion is covered with a third layer of titanium nitride doped with silicon.Type: ApplicationFiled: February 28, 2023Publication date: September 14, 2023Applicant: STMicroelectronics (Crolles 2) SASInventors: Marios BARLAS, Yannick LE FRIEC, Xavier FEDERSPIEL
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Publication number: 20230178479Abstract: A method is presented for manufacturing an insulated conductive via. The via crosses a first stack of layers to reach a first layer. A first cavity is formed partially extending into the first stack of layers. A second stack of layers is formed over the first stack of layers and in the first cavity. The second stack of layers includes an etch stop layer and an insulating layer. A second cavity is then formed extending completely through first and second stacks of layers to reach the first layer. An insulating liner then covers the walls and bottom of the second cavity. The insulating liner is then anisotropically etched, and the second cavity is filled by a conductive material forming the core of the via.Type: ApplicationFiled: December 5, 2022Publication date: June 8, 2023Applicant: STMicroelectronics (Crolles 2) SASInventors: Marios BARLAS, Pascal GOURAUD
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Publication number: 20230109590Abstract: A phase change filter is formed by an arrangement of dots, wherein each dot is made of a phase change material. A heating layer of electrically conductive material extends under the arrangement of dots. Current passing through the heating layer changes the dots between two states to alter attenuation of light passing through the filter.Type: ApplicationFiled: October 3, 2022Publication date: April 6, 2023Applicant: STMicroelectronics (Crolles 2) SASInventors: Marios BARLAS, Kirill SHIIANOV, Emmanuel JOSSE, Stephane MONFRAY
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Publication number: 20220085084Abstract: The present disclosure relates to a pixel comprising: a photodiode comprising a portion of a substrate of a semiconductor material, extending vertically from a first face of the substrate to a second face of the substrate configured to receive light; a layer of a first material covering each of the lateral surfaces of the portion; a layer of a second material covering the portion on the side of the first face, first and second material having refractive indexes lower than that of the semiconductor material; and a diffractive structure disposed on a face of the photodiode on the side of the second face.Type: ApplicationFiled: September 9, 2021Publication date: March 17, 2022Applicants: STMICROELECTRONICS (RESEARCH & DEVELOPMENT) LIMITED, STMicroelectronics (Crolles 2) SASInventors: Raul Andres BIANCHI, Marios BARLAS, Alexandre LOPEZ, Bastien MAMDY, Bruce RAE, Isobel NICHOLSON
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Publication number: 20220069217Abstract: Resistive memory cell provided with a first electrode and a second electrode arranged on either side of a dielectric layer and facing an interface between a first region and a second region, said first and second region having different compositions in terms of doping and/or dielectric constant, so as to confine the zone of reversible creation of a conductive filament at said interface.Type: ApplicationFiled: August 30, 2021Publication date: March 3, 2022Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVESInventors: Laurent GRENOUILLET, Marios BARLAS, Etienne NOWAK
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Publication number: 20220005850Abstract: An optoelectronic device includes a photodiode. At least a portion of an active area of the photodiode is separated from a neighboring photodiode by a first wall including a conductive core and an insulating sheath and by a second optical insulation wall. The first wall and second optical insulation wall further extend parallel to each other and separate the active area from a memory area of the photodiode.Type: ApplicationFiled: June 30, 2021Publication date: January 6, 2022Applicant: STMicroelectronics (Crolles 2) SASInventors: Alain INARD, Marios BARLAS
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Patent number: 11189792Abstract: A resistive non-volatile memory cell includes a first electrode, a second electrode and an oxide layer disposed between the first electrode and the second electrode, the memory cell being capable of reversibly switching between: —a high resistance state obtained by applying a first bias voltage between the first electrode and the second electrode; and—a low resistance state obtained by applying a second bias voltage between the first electrode and the second electrode; the oxide layer including a switching zone forming a conduction path prioritised for the current passing through the memory cell when the memory cell is in the low resistance state. The oxide layer includes a first zone doped with aluminium or silicon, the aluminium or silicon being present in the first zone with an atomic concentration that is selected so as to locate the switching zone outside the first zone.Type: GrantFiled: September 8, 2017Date of Patent: November 30, 2021Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVESInventors: Laurent Grenouillet, Marios Barlas, Philippe Blaise, Benoît Sklenard, Elisa Vianello
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Patent number: 10985317Abstract: A device for selecting a storage cell, includes a first electrode, a second electrode and an oxide layer disposed between the first electrode and the second electrode, wherein the oxide layer is doped with a first element from column IV of the periodic table.Type: GrantFiled: September 8, 2017Date of Patent: April 20, 2021Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVESInventors: Marios Barlas, Philippe Blaise, Laurent Grenouillet, Benoît Sklenard, Elisa Vianello
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Publication number: 20200127199Abstract: A device for selecting a storage cell, includes a first electrode, a second electrode and an oxide layer disposed between the first electrode and the second electrode, wherein the oxide layer is doped with a first element from column IV of the periodic table.Type: ApplicationFiled: September 8, 2017Publication date: April 23, 2020Inventors: Mario BARLAS, Philippe BLAISE, Laurent GRENOUILLET, Benoît SKLENARD, Elisa VIANELLO
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Patent number: 10446564Abstract: The invention relates to a non-volatile memory that comprises selection transistors. Each selection transistor includes a layer of semiconductor material with a channel region and conduction electrodes, a gate stack including a gate electrode and a gate insulator, an isolation trench between the transistors, a storage structure of the RRAM type comprising a control electrode, and a dielectric layer formed under the control electrode and in the same material as the gate insulator, comprising a central part directly above the isolation trench and ends extending directly above conduction electrodes, and configured so as to form conducting filaments. The said storage structure and the said selection transistors are formed in the same pre-metallization layer.Type: GrantFiled: May 11, 2018Date of Patent: October 15, 2019Assignees: Commissariat a l'energie atomique et aux energies alternatives, Universite d'Aix-MarseilleInventors: Jean-Michel Portal, Marios Barlas, Laurent Grenouillet, Elisa Vianello
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Publication number: 20190280203Abstract: A resistive non-volatile memory cell includes a first electrode, a second electrode and an oxide layer disposed between the first electrode and the second electrode, the memory cell being capable of reversibly switching between: —a high resistance state obtained by applying a first bias voltage between the first electrode and the second electrode; and—a low resistance state obtained by applying a second bias voltage between the first electrode and the second electrode; the oxide layer including a switching zone forming a conduction path prioritised for the current passing through the memory cell when the memory cell is in the low resistance state. The oxide layer includes a first zone doped with aluminium or silicon, the aluminium or silicon being present in the first zone with an atomic concentration that is selected so as to locate the switching zone outside the first zone.Type: ApplicationFiled: September 8, 2017Publication date: September 12, 2019Inventors: Laurent GRENOUILLET, Marios BARLAS, Philippe BLAISE, Benoît SKLENARD, Elisa VIANELLO
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Publication number: 20190173005Abstract: A method for fabricating an OxRAM type memory location, including the steps of providing a stack including a superposition of a first layer that includes a first material made of Ti at more than 30% by mole fraction; a second layer made of HfO2 positioned under the first layer; via an ion implantation of a second material chosen from Xe, Kr or Ar in the first layer, carrying out an implantation of the first material in the second layer by collision with recoil effect in the first layer.Type: ApplicationFiled: December 5, 2018Publication date: June 6, 2019Applicant: Commissariat a I'energie atomique et aux energies alternativesInventors: Marios Barlas, Philippe Blaise, Laurent Grenouillet, Boubacar Traore
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Publication number: 20180331115Abstract: The invention relates to a non-volatile memory that comprises selection transistors. Each selection transistor includes a layer of semiconductor material with a channel region and conduction electrodes, a gate stack including a gate electrode and a gate insulator, an isolation trench between the transistors, a storage structure of the RRAM type comprising a control electrode, and a dielectric layer formed under the control electrode and in the same material as the gate insulator, comprising a central part directly above the isolation trench and ends extending directly above conduction electrodes, and configured so as to form conducting filaments. The said storage structure and the said selection transistors are formed in the same pre-metallization layer.Type: ApplicationFiled: May 11, 2018Publication date: November 15, 2018Applicants: Commissariat a l'energie atomique et aux energies alternatives, Universite d'Aix-MarseilleInventors: Jean-Michel Portal, Marios Barlas, Laurent Grenouillet, Elisa Vianello