Patents by Inventor Maristella Spella

Maristella Spella has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11837560
    Abstract: A method of manufacturing a semiconductor device is provided. The method includes forming an assembly including placing a semiconductor die and a launcher structure on a carrier substrate, encapsulating at least a portion of the semiconductor die and the launcher structure, and applying a redistribution layer on a surface of the semiconductor die and a surface of the launcher structure to connect a bond pad of the semiconductor die with an antenna launcher of the launcher structure. The assembly is attached to a substrate and a waveguide overlapping the assembly is attached to the substrate. The waveguide structure is physically decoupled from the assembly.
    Type: Grant
    Filed: August 26, 2021
    Date of Patent: December 5, 2023
    Assignee: NXP USA, INC.
    Inventors: Michael B. Vincent, Giorgio Carluccio, Maristella Spella, Scott M. Hayes
  • Patent number: 11777204
    Abstract: A package includes an integrated circuit, IC, die having circuitry configured to generate signalling for transmission to a waveguide and/or receive signalling from a waveguide via a launcher. The die is coupled to an interconnect layer extending out from a footprint of the die. The launcher is formed in a launcher-substrate, separate from the die. The launcher is coupled to the die to pass the signalling therebetween by a connection in the interconnect layer. The launcher includes a launcher element mounted in a first plane within the launcher-substrate and a waveguide-cavity including a ground plane arranged opposed to and spaced from the first plane. The waveguide-cavity is further defined by at least one side wall extending from the ground plane towards the first plane. The die and launcher are at least partially surrounded by mould material of the package.
    Type: Grant
    Filed: November 2, 2021
    Date of Patent: October 3, 2023
    Assignee: NXP B.V.
    Inventors: Giorgio Carluccio, Michael B. Vincent, Maristella Spella, Antonius Johannes Matheus de Graauw, Harshitha Thippur Shivamurthy
  • Patent number: 11631625
    Abstract: A mechanism is provided to remove heat from an integrated circuit (IC) device die by directing heat through a waveguide to a heat sink. The waveguide is mounted on top of a package containing the IC device die. The waveguide is thermally coupled to the IC device die. The waveguide transports the heat to a heat sink coupled to the waveguide and located adjacent to the package on top of a printed circuit board on which the package is mounted. Embodiments provide both thermal dissipation of the generated heat while at the same time maintaining good radio frequency performance of the waveguide.
    Type: Grant
    Filed: August 17, 2022
    Date of Patent: April 18, 2023
    Assignee: NXP USA, INC.
    Inventors: Michael B. Vincent, Antonius Johannes Matheus de Graauw, Giorgio Carluccio, Waqas Hassan Syed, Maristella Spella
  • Publication number: 20220392821
    Abstract: A mechanism is provided to remove heat from an integrated circuit (IC) device die by directing heat through a waveguide to a heat sink. The waveguide is mounted on top of a package containing the IC device die. The waveguide is thermally coupled to the IC device die. The waveguide transports the heat to a heat sink coupled to the waveguide and located adjacent to the package on top of a printed circuit board on which the package is mounted. Embodiments provide both thermal dissipation of the generated heat while at the same time maintaining good radio frequency performance of the waveguide.
    Type: Application
    Filed: August 17, 2022
    Publication date: December 8, 2022
    Applicant: NXP USA, Inc.
    Inventors: Michael B. Vincent, Antonius Johannes Matheus de Graauw, Giorgio Carluccio, Waqas Hassan Syed, Maristella Spella
  • Patent number: 11456227
    Abstract: A mechanism is provided to remove heat from an integrated circuit (IC) device die by directing heat through a waveguide to a heat sink. The waveguide is mounted on top of a package containing the IC device die. The waveguide is thermally coupled to the IC device die. The waveguide transports the heat to a heat sink coupled to the waveguide and located adjacent to the package on top of a printed circuit board on which the package is mounted. Embodiments provide both thermal dissipation of the generated heat while at the same time maintaining good radio frequency performance of the waveguide.
    Type: Grant
    Filed: December 17, 2019
    Date of Patent: September 27, 2022
    Assignee: NXP USA, INC.
    Inventors: Michael B. Vincent, Antonius Johannes Matheus de Graauw, Giorgio Carluccio, Waqas Hassan Syed, Maristella Spella
  • Patent number: 11415626
    Abstract: A method of testing a semiconductor device. An apparatus comprising a semiconductor device and a test apparatus. The semiconductor device includes an integrated circuit and a plurality of external radiating elements at a surface of the device, the radiating elements include transmit elements and receive elements. The test apparatus includes a surface for placing against the surface of the device. The test apparatus also includes at least one waveguide, which extends through the test apparatus for routing electromagnetic radiation transmitted by one of the transmit elements of the device to one of the receive elements of the device. Each waveguide comprises a plurality of waveguide openings for coupling electromagnetically to corresponding radiating elements of the plurality of radiating elements located at the surface of the device. A spacing between the waveguide openings of each waveguide is larger than, or smaller than a spacing between the corresponding radiating elements.
    Type: Grant
    Filed: December 11, 2020
    Date of Patent: August 16, 2022
    Assignee: NXP B.V.
    Inventors: Jan-Peter Schat, Abdellatif Zanati, Henrik Asendorf, Maristella Spella, Waqas Hassan Syed, Giorgio Carluccio, Antonius Johannes Matheus de Graauw
  • Publication number: 20220231408
    Abstract: A package comprising, an integrated circuit, IC, die comprising circuitry configured to generate signalling for transmission to a waveguide and/or receive signalling from a waveguide via a launcher, the die coupled to an interconnect layer extending out from a footprint of the die; and the launcher is formed in a launcher-substrate, separate from the die, the launcher coupled to the die to pass said signalling therebetween by a connection in said interconnect layer, wherein said launcher comprises a launcher element mounted in a first plane within the launcher-substrate and a waveguide-cavity comprising a ground plane arranged opposed to and spaced from the first plane, the waveguide-cavity further defined by at least one side wall extending from the ground plane towards the first plane; and wherein said die and said launcher are at least partially surrounded by mould material of said package.
    Type: Application
    Filed: November 2, 2021
    Publication date: July 21, 2022
    Inventors: Giorgio Carluccio, Michael B. Vincent, Maristella Spella, Antonius Johannes Matheus de Graauw, Harshitha Thippur Shivamurthy
  • Patent number: 11276654
    Abstract: A mechanism is provided to remove heat from an integrated circuit (IC) device die by directing heat through a waveguide to a heat sink. Embodiments provide the waveguide mounted on top of a package containing the IC device die. The waveguide is thermally coupled to the IC device die. The waveguide transports the heat to a heat sink coupled to the waveguide and located adjacent to the package on top of a printed circuit board on which the package is mounted. Embodiments provide both thermal dissipation of the generated heat while at the same time maintaining good radio frequency (RF) performance of the waveguide.
    Type: Grant
    Filed: December 17, 2019
    Date of Patent: March 15, 2022
    Assignee: NXP USA, INC.
    Inventors: Michael B. Vincent, Antonius Johannes Matheus de Graauw, Giorgio Carluccio, Waqas Hassan Syed, Maristella Spella
  • Publication number: 20210391285
    Abstract: A method of manufacturing a semiconductor device is provided. The method includes forming an assembly including placing a semiconductor die and a launcher structure on a carrier substrate, encapsulating at least a portion of the semiconductor die and the launcher structure, and applying a redistribution layer on a surface of the semiconductor die and a surface of the launcher structure to connect a bond pad of the semiconductor die with an antenna launcher of the launcher structure. The assembly is attached to a substrate and a waveguide overlapping the assembly is attached to the substrate. The waveguide structure is physically decoupled from the assembly.
    Type: Application
    Filed: August 26, 2021
    Publication date: December 16, 2021
    Inventors: Michael B. Vincent, Giorgio Carluccio, Maristella Spella, Scott M. Hayes
  • Patent number: 11133273
    Abstract: A method of manufacturing a semiconductor device is provided. The method includes forming an assembly including placing a semiconductor die and a launcher structure on a carrier substrate, encapsulating at least a portion of the semiconductor die and the launcher structure, and applying a redistribution layer on a surface of the semiconductor die and a surface of the launcher structure to connect a bond pad of the semiconductor die with an antenna launcher of the launcher structure. The assembly is attached to a substrate and a waveguide overlapping the assembly is attached to the substrate. The waveguide structure is physically decoupled from the assembly.
    Type: Grant
    Filed: December 17, 2019
    Date of Patent: September 28, 2021
    Assignee: NXP USA, INC.
    Inventors: Michael B. Vincent, Giorgio Carluccio, Maristella Spella, Scott M. Hayes
  • Publication number: 20210239754
    Abstract: A method of testing a semiconductor device. An apparatus comprising a semiconductor device and a test apparatus. The semiconductor device includes an integrated circuit and a plurality of external radiating elements at a surface of the device, the radiating elements include transmit elements and receive elements. The test apparatus includes a surface for placing against the surface of the device. The test apparatus also includes at least one waveguide, which extends through the test apparatus for routing electromagnetic radiation transmitted by one of the transmit elements of the device to one of the receive elements of the device. Each waveguide comprises a plurality of waveguide openings for coupling electromagnetically to corresponding radiating elements of the plurality of radiating elements located at the surface of the device. A spacing between the waveguide openings of each waveguide is larger than, or smaller than a spacing between the corresponding radiating elements.
    Type: Application
    Filed: December 11, 2020
    Publication date: August 5, 2021
    Inventors: Jan-Peter Schat, Abdellatif Zanati, Henrik Asendorf, Maristella Spella, Waqas Hassan Syed, Giorgio Carluccio, Antonius Johannes Matheus de Graauw
  • Publication number: 20210183796
    Abstract: A method of manufacturing a semiconductor device is provided. The method includes forming an assembly including placing a semiconductor die and a launcher structure on a carrier substrate, encapsulating at least a portion of the semiconductor die and the launcher structure, and applying a redistribution layer on a surface of the semiconductor die and a surface of the launcher structure to connect a bond pad of the semiconductor die with an antenna launcher of the launcher structure. The assembly is attached to a substrate and a waveguide overlapping the assembly is attached to the substrate. The waveguide structure is physically decoupled from the assembly.
    Type: Application
    Filed: December 17, 2019
    Publication date: June 17, 2021
    Inventors: MICHAEL B. VINCENT, Giorgio Carluccio, Maristella Spella, Scott M. Hayes
  • Publication number: 20210183725
    Abstract: A mechanism is provided to remove heat from an integrated circuit (IC) device die by directing heat through a waveguide to a heat sink. The waveguide is mounted on top of a package containing the IC device die. The waveguide is thermally coupled to the IC device die. The waveguide transports the heat to a heat sink coupled to the waveguide and located adjacent to the package on top of a printed circuit board on which the package is mounted. Embodiments provide both thermal dissipation of the generated heat while at the same time maintaining good radio frequency performance of the waveguide.
    Type: Application
    Filed: December 17, 2019
    Publication date: June 17, 2021
    Applicant: NXP USA, Inc.
    Inventors: Michael B. Vincent, Antonius Johannes Matheus de Graauw, Giorgio Carluccio, Waqas Hassan Syed, Maristella Spella
  • Publication number: 20210183797
    Abstract: A mechanism is provided to remove heat from an integrated circuit (IC) device die by directing heat through a waveguide to a heat sink. Embodiments provide the waveguide mounted on top of a package containing the IC device die. The waveguide is thermally coupled to the IC device die. The waveguide transports the heat to a heat sink coupled to the waveguide and located adjacent to the package on top of a printed circuit board on which the package is mounted. Embodiments provide both thermal dissipation of the generated heat while at the same time maintaining good radio frequency (RF) performance of the waveguide.
    Type: Application
    Filed: December 17, 2019
    Publication date: June 17, 2021
    Applicant: NXP USA, Inc.
    Inventors: Michael B. Vincent, Antonius Johannes Matheus de Graauw, Giorgio Carluccio, Waqas Hassan Syed, Maristella Spella
  • Patent number: 10615134
    Abstract: An integrated circuit package is described comprising an integrated circuit die and an antenna structure coupled to the integrated circuit die and comprising a stacked arrangement of metal and dielectric layers, wherein a first metal layer includes a planar antenna and at least one further metal layer comprises an artificial dielectric layer. The integrated circuit package may improve the directionality of the antenna and reduces the sensitivity of the antenna to the printed circuit board on which the integrated circuit package is mounted.
    Type: Grant
    Filed: January 15, 2018
    Date of Patent: April 7, 2020
    Assignee: NXP B.V.
    Inventors: Maristella Spella, Waqas Hassan Syed, Daniele Cavallo, Mingda Huang, Leo Van Gemert
  • Publication number: 20180233465
    Abstract: An integrated circuit package is described comprising an integrated circuit die and an antenna structure coupled to the integrated circuit die and comprising a stacked arrangement of metal and dielectric layers, wherein a first metal layer includes a planar antenna and at least one further metal layer comprises an artificial dielectric layer. The integrated circuit package may improve the directionality of the antenna and reduces the sensitivity of the antenna to the printed circuit board on which the integrated circuit package is mounted.
    Type: Application
    Filed: January 15, 2018
    Publication date: August 16, 2018
    Inventors: Maristella SPELLA, Waqas Hassan SYED, Daniele CAVALLO, Mingda HUANG, Leo VAN GEMERT
  • Patent number: 9608334
    Abstract: A device is described. The device includes a chip, a reflector, and an antenna. The reflector is disposed on a surface of the chip. The reflector is a metalized layer on the surface of the chip.
    Type: Grant
    Filed: March 31, 2014
    Date of Patent: March 28, 2017
    Assignee: NXP B.V.
    Inventor: Maristella Spella
  • Patent number: 9515368
    Abstract: One example discloses a transmission line interconnect, comprising: an antenna coupling surface; a transmission line coupling surface; and a dielectric molding compound electromagnetically coupling the antenna coupling surface to the transmission line coupling surface. Another example discloses a method of manufacture, for a transmission line interconnect, comprising: forming a dielectric molding compound; defining an antenna coupling surface on the dielectric molding compound; and defining a transmission line coupling surface on the dielectric molding compound whereby millimeter wave frequencies received at the antenna coupling surface are electromagnetically coupled to the transmission line coupling surface.
    Type: Grant
    Filed: March 11, 2014
    Date of Patent: December 6, 2016
    Assignee: NXP B.V.
    Inventors: Maristella Spella, Raf Lodewijk Jan Roovers
  • Publication number: 20150280327
    Abstract: A device is described. The device includes a chip, a reflector, and an antenna. The reflector is disposed on a surface of the chip. The reflector is a metalized layer on the surface of the chip.
    Type: Application
    Filed: March 31, 2014
    Publication date: October 1, 2015
    Applicant: NXP B.V.
    Inventor: Maristella Spella
  • Publication number: 20150263403
    Abstract: One example discloses a transmission line interconnect, comprising: an antenna coupling surface; a transmission line coupling surface; and a dielectric molding compound electromagnetically coupling the antenna coupling surface to the transmission line coupling surface. Another example discloses a method of manufacture, for a transmission line interconnect, comprising: forming a dielectric molding compound; defining an antenna coupling surface on the dielectric molding compound; and defining a transmission line coupling surface on the dielectric molding compound whereby millimeter wave frequencies received at the antenna coupling surface are electromagnetically coupled to the transmission line coupling surface.
    Type: Application
    Filed: March 11, 2014
    Publication date: September 17, 2015
    Applicant: NXP B.V.
    Inventors: Maristella Spella, Raf Lodewijk Jan Roovers