Patents by Inventor Marites Roque

Marites Roque has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20260240021
    Abstract: A semiconductor device has an electrical component and an e-bar structure disposed to a side of the electrical component. An encapsulant is deposited over the electrical component and e-bar structure. An RDL is formed over the electrical component, encapsulant, and e-bar structure. The e-bar structure has a core layer, a first conductive layer formed over a first surface of the core layer, and a second conductive layer formed over a second surface of the core layer. The second conductive layer includes a thickness greater than the first conductive layer. The RDL has an insulating layer formed over the electrical component and encapsulant, and a conductive layer formed over the insulating layer. A bump is formed over a contact pad of the e-bar structure opposite the RDL. A contact pad of the electrical component is electrically connected to the RDL opposite the bump.
    Type: Application
    Filed: March 31, 2026
    Publication date: August 13, 2026
    Applicant: STATS ChipPAC Pte. Ltd.
    Inventors: Linda Pei Ee Chua, Kai Chong Chan, Rowena Zarate, Marites Roque, Yi Jing Eric Chong
  • Patent number: 12616048
    Abstract: A semiconductor device has an electrical component and an e-bar structure disposed to a side of the electrical component. An encapsulant is deposited over the electrical component and e-bar structure. An RDL is formed over the electrical component, encapsulant, and e-bar structure. The e-bar structure has a core layer, a first conductive layer formed over a first surface of the core layer, and a second conductive layer formed over a second surface of the core layer. The second conductive layer includes a thickness greater than the first conductive layer. The RDL has an insulating layer formed over the electrical component and encapsulant, and a conductive layer formed over the insulating layer. A bump is formed over a contact pad of the e-bar structure opposite the RDL. A contact pad of the electrical component is electrically connected to the RDL opposite the bump.
    Type: Grant
    Filed: June 30, 2023
    Date of Patent: April 28, 2026
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: Linda Pei Ee Chua, Kai Chong Chan, Rowena Zarate, Marites Roque, Yi Jing Eric Chong
  • Publication number: 20260068573
    Abstract: A method for grinding a wafer is provided. The method comprises: providing a wafer having a back side and a front side opposite to the back side, wherein the wafer further comprises a central zone for accommodating semiconductor units and a peripheral zone surrounding the central zone; forming a trench within the peripheral zone and extending along substantially an entire circumference of the peripheral zone, wherein the trench is exposed from the front side of the wafer; filling the trench with a filler to form a spacer ring within the peripheral zone, wherein the spacer ring isolates the central zone from an edge of the wafer; attaching the wafer onto a platform at the front side of the wafer; and grinding the wafer from the back side of the wafer.
    Type: Application
    Filed: September 4, 2025
    Publication date: March 5, 2026
    Inventors: YiJing Eric CHONG, Rowena ZARATE, Marites ROQUE, PeiEe Linda CHUA
  • Publication number: 20260001190
    Abstract: A wafer grinding method comprises: providing a wafer base comprising a front side and a back side, wherein the front side comprises a solder ball area and an annular peripheral area surrounding the solder ball area; forming a patterned photoresist layer on the front side of the wafer base, wherein the patterned photoresist layer at least partially covers the annular peripheral area but exposes the solder ball area; forming solder balls on the solder ball area; attaching a back grinding tape on the front side to cover both the solder ball area and the annular peripheral area; and performing a back grinding process on the back side of the wafer base.
    Type: Application
    Filed: June 24, 2025
    Publication date: January 1, 2026
    Inventors: YiJing Eric CHONG, Rowena ZARATE, Marites ROQUE, PeiEe Linda CHUA, KaiChong CHAN
  • Publication number: 20250343195
    Abstract: A semiconductor device has a semiconductor die and an encapsulant deposited over the semiconductor die. An interconnect structure is formed over the semiconductor die and encapsulant. A first under-bump metallization (UBM) pad is formed over the interconnect structure. The first UBM pad is non-circular. A stencil is disposed over the first UBM pad. The stencil includes a first opening over the first UBM pad with a footprint of the first opening larger than a footprint of the first UBM pad. A solder paste is deposited in the first opening. The solder paste is reflowed to form a solder bump on the UBM pad.
    Type: Application
    Filed: May 6, 2024
    Publication date: November 6, 2025
    Applicant: STATS ChipPAC Pte. Ltd.
    Inventors: Linda Pei Ee Chua, Rowena Zarate, Kai Chong Chan, Jian Zuo, Marites Roque, Eric Yi Jing Chong
  • Publication number: 20250219006
    Abstract: A semiconductor device has a first semiconductor die and a first insulating layer formed over the first semiconductor die. A trench is formed in the first insulating layer. A second insulating layer is formed over the first insulating layer. A recess forms in the second insulating layer over the trench automatically as part of the formation process of the second insulating layer. A second semiconductor die is mounted over the second insulating layer. The recess completely surrounds the second semiconductor die in plan view. An underfill is dispensed between the first semiconductor die and second semiconductor die.
    Type: Application
    Filed: January 3, 2024
    Publication date: July 3, 2025
    Applicant: STATS ChipPAC Pte. Ltd.
    Inventors: Marites Roque, Linda Pei Ee Chua, Rowena Zarate, Yi Jing Eric Chong, Kai Chong Chan
  • Publication number: 20250118643
    Abstract: A semiconductor device has a first substrate with a surface. A thickness of the first substrate is less than 120 micrometers. The surface undergoes a grinding operation. The surface of the first substrate is then polished to produce a polished surface. The first substrate is singulated into a plurality of semiconductor die. The semiconductor die is over an interposer. The interposer has a second substrate and a conductive via formed through the second substrate. The interposer further has a first insulating layer formed over a first surface of the second substrate, first conductive layer formed over the first surface, second insulating layer formed over a second surface of the second substrate, second conductive layer formed over the second surface, and bump formed over the second conductive layer. An underfill material is deposited around the semiconductor die. The polished surface inhibits progression of the underfill material onto the polished surface.
    Type: Application
    Filed: October 9, 2023
    Publication date: April 10, 2025
    Applicant: STATS ChipPAC Pte. Ltd.
    Inventors: Yi Jing Eric Chong, Marites Roque, Rowena Zarate, Linda Pei Ee Chua, Kai Chong Chan
  • Publication number: 20250006608
    Abstract: A semiconductor device has an electrical component and an e-bar structure disposed to a side of the electrical component. An encapsulant is deposited over the electrical component and e-bar structure. An RDL is formed over the electrical component, encapsulant, and e-bar structure. The e-bar structure has a core layer, a first conductive layer formed over a first surface of the core layer, and a second conductive layer formed over a second surface of the core layer. The second conductive layer includes a thickness greater than the first conductive layer. The RDL has an insulating layer formed over the electrical component and encapsulant, and a conductive layer formed over the insulating layer. A bump is formed over a contact pad of the e-bar structure opposite the RDL. A contact pad of the electrical component is electrically connected to the RDL opposite the bump.
    Type: Application
    Filed: June 30, 2023
    Publication date: January 2, 2025
    Applicant: STATS ChipPAC Pte. Ltd.
    Inventors: Linda Pei Ee Chua, Kai Chong Chan, Rowena Zarate, Marites Roque, Yi Jing Eric Chong