Abstract: Memory is allocated according to lifespan. The memory manager allocates requests for short-term memory to one portion of memory and allocates requests for long-term memory to another portion of the memory. The memory manager looks for free space for requests for long-term memory starting at a first location in the memory and the memory manager looks for free space beginning at a second location in the memory for requests for short-term memory. In that way, more memory banks are likely to be free and can be powered down to save power consumption, particularly during sleep states.

Abstract: A system for securing the contents of an external nonvolatile memory associated with a main processing device is disclosed. The system stores additional information associated with each cache line in the nonvolatile memory. In some embodiments, this additional information comprises a NONCE (number used once) and a MAC (Message Authentication Code). When the main processing device reads a cache line from the nonvolatile memory, the NONCE, address and data from the cache line are used to generate a MAC, which is then compared to the MAC stored in the nonvolatile memory. If the MACs match, the cache line is stored in the on-board cache of the main processing device. If the MACs do not match, a countermeasure may be implemented. The use of a NONCE addresses an information leakage issue that is present when stream ciphers, such as AES-CTR or AES-GCM, are used in data storage applications.

Abstract: A non-volatile memory (NVM) driver includes a function library with native function calls and a hardware abstraction layer for receiving at least one instruction from the function library and providing signals to cause an NVM to execute the at least one instruction. The NVM includes a plurality of sectors, and the NVM driver uses a first portion as an application visible memory, and a second portion for another purpose. The NVM driver maintains the NVM as a circular buffer within the application visible memory. When a native function call is a resizing command, the function library adjusts the circular buffer selectively according to whether the resizing command increases or decreases the application visible memory. When a native function call is a write counter command, the NVM driver selectively creates a new counter object including a counter base and a plurality of increment locations using a next location pointer.

Abstract: In one form, a non-volatile memory driver includes a function library defining a plurality of native function calls, and a hardware abstraction layer having an input coupled to and output of the function library for receiving the at least one instruction, and an output for providing a plurality of signals to cause a non-volatile memory to execute the at least one instruction. The non-volatile memory driver maintains the flash memory as a circular buffer using a bottom sector pointer and a next location pointer. In response to receiving a housekeeping command generated from corresponding command from an application layer as the selected native function call, the function library causes the hardware abstraction layer to selectively repack valid data of a bottom sector indicated by said bottom sector pointer using the next location pointer, and to selectively erase the bottom sector.

Abstract: A non-volatile memory (NVM) driver includes a function library with native function calls and a hardware abstraction layer for receiving at least one instruction from the function library and providing signals to cause an NVM to execute the at least one instruction. The NVM includes a plurality of sectors, and the NVM driver uses a first portion as an application visible memory, and a second portion for another purpose. The NVM driver maintains the NVM as a circular buffer within the application visible memory. When a native function call is a resizing command, the function library adjusts the circular buffer selectively according to whether the resizing command increases or decreases the application visible memory. When a native function call is a write counter command, the NVM driver selectively creates a new counter object including a counter base and a plurality of increment locations using a next location pointer.

Abstract: In one form, a non-volatile memory driver includes a function library defining a plurality of native function calls, and a hardware abstraction layer having an input coupled to and output of the function library for receiving the at least one instruction, and an output for providing a plurality of signals to cause a non-volatile memory to execute the at least one instruction. The non-volatile memory driver maintains the flash memory as a circular buffer using a bottom sector pointer and a next location pointer. In response to receiving a housekeeping command generated from corresponding command from an application layer as the selected native function call, the function library causes the hardware abstraction layer to selectively repack valid data of a bottom sector indicated by said bottom sector pointer using the next location pointer, and to selectively erase the bottom sector.

Abstract: An apparatus includes a processor and a loop cache coupled to the processor. The loop cache provides to the processor instructions corresponding to a loop in the instructions. The loop cache includes a persistence counter.

Abstract: A processor, such as a low-cost microcontroller unit, uses a DMA controller to facilitate direct memory transactions between hardware subsystems independently of the CPU. To enable those transactions to be carried out security, gateways are provided to the DMA controller and peripheral bridge. The gateways, which have access to multiple access policies, switch between those policies depending on a hardware context and/or subcontext, such as the bus master originating the transaction and/or the DMA channel associated with the transaction. The gateways are operable to administer those policies independently of the CPU. In various implementations, gateways are provided for the DMA controller, the peripheral bridge, and/or individual peripherals. The processor is able to support secure, fully containerized operations involving its peripherals without constant CPU intervention.

Abstract: An apparatus includes a processor and a loop cache coupled to the processor. The loop cache provides to the processor instructions corresponding to a loop in the instructions. The loop cache includes a persistence counter.

Abstract: A processor, such as a low-cost microcontroller unit, uses a DMA controller to facilitate direct memory transactions between hardware subsystems independently of the CPU. To enable those transactions to be carried out security, gateways are provided to the DMA controller and peripheral bridge. The gateways, which have access to multiple access policies, switch between those policies depending on a hardware context and/or subcontext, such as the bus master originating the transaction and/or the DMA channel associated with the transaction. The gateways are operable to administer those policies independently of the CPU. In various implementations, gateways are provided for the DMA controller, the peripheral bridge, and/or individual peripherals. The processor is able to support secure, fully containerized operations involving its peripherals without constant CPU intervention.