Abstract: A circuit includes a receiver configured to couple to an antenna, configured to have a wakeup mode and an active mode, and to transition from the wakeup mode to the active mode in response to a wakeup signal received through the antenna. The receiver includes an impedance matching circuit coupled with the antenna, a low-noise amplifier coupled with the impedance matching circuit, a mixer coupled with the low-noise amplifier, a radio-frequency reference clock generator coupled with the mixer, a low-pass filter coupled with the mixer, an analog-to digital-converter coupled with the low-pass filter, and a control circuit configured to transition the receiver from the wakeup mode to the active mode in response to the wakeup signal. The low-noise amplifier, the mixer, the radio frequency reference clock generator, and the analog-to-digital converter are configured to be duty-cycled between a sleep state and an active wakeup receive state during the wakeup mode.

Abstract: Using a phase interferometry method which utilizes both amplitude and phase allows the determination and estimation of multipath signals. To determine the location of an object, a signal that contains sufficient information to allow determination of both amplitude and phase, like a packet that includes a sinewave portion, is provided from a master device. A slave device measures the phase and amplitude of the received packet and returns this information to the master device. The slave device returns a packet to the master that contains a similar sinewave portion to allow the master device to determine the phase and amplitude of the received signals. Based on the two sets of amplitude and phase of the RF signals, the master device utilizes a fast Fourier transform or techniques like multiple signal classification to determine the indicated distance for each path and thus more accurately determines a location of the slave device.

Abstract: In described examples, an electronic circuit for determining a phase difference between a first clock signal and a second clock signal includes a timer circuit, circuitry for generating a selectively delayed transition of the second clock signal, and phase determination circuitry. The timer circuit produces an elapsed time between a transition of the first clock signal and the selectively delayed transition of the second clock signal. The circuitry for generating the selectively delayed transition of the second clock signal generates the selectively delayed transition in response to a random selection of a respective output from a plurality of second clock signal delay stages. The phase determination circuitry provides the phase difference in response to the elapsed time and the random selection of a respective output from a plurality of second clock signal delay stages.

Abstract: A circuit for a phase-locked loop is described herein. The circuit includes a phase frequency detector configured to determine a phase error, a loop filter coupled to the phase frequency detector and configured to provide a clock control signal based on the phase error, and a controller coupled to the phase frequency detector and to the loop filter. The controller is configured to receive the phase error, detect a behavior of the phase error, and, responsive to the behavior of the phase error, perform a response that includes causing the phase frequency detector to adjust the phase error and causing the loop filter to adjust the clock control signal. Thus, the circuit may reduce settling time, overshoot, and/or undershoot in an output clock generated based on the clock control signal.

Abstract: In described examples, an electronic circuit for determining a phase difference between a first clock signal and a second clock signal includes a timer circuit, circuitry for generating a selectively delayed transition of the second clock signal, and phase determination circuitry. The timer circuit produces an elapsed time between a transition of the first clock signal and the selectively delayed transition of the second clock signal. The circuitry for generating the selectively delayed transition of the second clock signal generates the selectively delayed transition in response to a random selection of a respective output from a plurality of second clock signal delay stages. The phase determination circuitry provides the phase difference in response to the elapsed time and the random selection of a respective output from a plurality of second clock signal delay stages.

Abstract: Aspects of the disclosure provide for an apparatus comprising a time-to-digital converter (TDC) and a processor coupled to the TDC. In some examples, the TDC may be configured to receive a signal and generate a measurement result indicating a time between start and stop events of the signal. The processor may be configured to receive the measurement result, compare the measurement result to a target value, and determine a non-linearity model configured to correct a variance of the measurement result from the target value.

Abstract: Aspects of the disclosure provide for an apparatus comprising a time-to-digital converter (TDC) and a processor coupled to the TDC. In some examples, the TDC may be configured to receive a signal and generate a measurement result indicating a time between start and stop events of the signal. The processor may be configured to receive the measurement result, compare the measurement result to a target value, and determine a non-linearity model configured to correct a variance of the measurement result from the target value.

Abstract: A technique of separating a sequence of modulation shift keying (MSK) symbols into a first portion and a second portion and separately comparing the first portion of the sequence of MSK symbols and the second portion of the sequence of MSK symbols against a first portion of a reference sequence of MSK symbols and a second portion of the reference sequence of MSK symbols allows a low complexity detection of a start field delimiter in a wireless communication packet.

Abstract: In described examples, an electronic circuit for determining a phase difference between a first clock signal and a second clock signal includes a timer circuit, circuitry for generating a selectively delayed transition of the second clock signal, and phase determination circuitry. The timer circuit produces an elapsed time between a transition of the first clock signal and the selectively delayed transition of the second clock signal. The circuitry for generating the selectively delayed transition of the second clock signal generates the selectively delayed transition in response to a random selection of a respective output from a plurality of second clock signal delay stages. The phase determination circuitry provides the phase difference in response to the elapsed time and the random selection of a respective output from a plurality of second clock signal delay stages.

Abstract: In described examples, an electronic circuit for determining a phase difference between a first clock signal and a second clock signal includes a timer circuit, circuitry for generating a selectively delayed transition of the second clock signal, and phase determination circuitry. The timer circuit produces an elapsed time between a transition of the first clock signal and the selectively delayed transition of the second clock signal. The circuitry for generating the selectively delayed transition of the second clock signal generates the selectively delayed transition in response to a random selection of a respective output from a plurality of second clock signal delay stages. The phase determination circuitry provides the phase difference in response to the elapsed time and the random selection of a respective output from a plurality of second clock signal delay stages.

Abstract: Aspects of the disclosure provide for an apparatus comprising a time-to-digital converter (TDC) and a processor coupled to the TDC. In some examples, the TDC may be configured to receive a signal and generate a measurement result indicating a time between start and stop events of the signal. The processor may be configured to receive the measurement result, compare the measurement result to a target value, and determine a non-linearity model configured to correct a variance of the measurement result from the target value.

Abstract: Using a phase interferometry method which utilizes both amplitude and phase allows the determination and estimation of multipath signals. To determine the location of an object, a signal that contains sufficient information to allow determination of both amplitude and phase, like a packet that includes a sinewave portion, is provided from a master device. A slave device measures the phase and amplitude of the received packet and returns this information to the master device. The slave device returns a packet to the master that contains a similar sinewave portion to allow the master device to determine the phase and amplitude of the received signals. Based on the two sets of amplitude and phase of the RF signals, the master device utilizes a fast Fourier transform or techniques like multiple signal classification to determine the indicated distance for each path and thus more accurately determines a location of the slave device.

Abstract: In described examples, an electronic circuit for determining a phase difference between a first clock signal and a second clock signal includes a timer circuit, circuitry for generating a selectively delayed transition of the second clock signal, and phase determination circuitry. The timer circuit produces an elapsed time between a transition of the first clock signal and the selectively delayed transition of the second clock signal. The circuitry for generating the selectively delayed transition of the second clock signal generates the selectively delayed transition in response to a random selection of a respective output from a plurality of second clock signal delay stages. The phase determination circuitry provides the phase difference in response to the elapsed time and the random selection of a respective output from a plurality of second clock signal delay stages.

Abstract: A technique of separating a sequence of modulation shift keying (MSK) symbols into a first portion and a second portion and separately comparing the first portion of the sequence of MSK symbols and the second portion of the sequence of MSK symbols against a first portion of a reference sequence of MSK symbols and a second portion of the reference sequence of MSK symbols allows a low complexity detection of a start field delimiter in a wireless communication packet.

Abstract: In described examples, an electronic circuit for determining a phase difference between a first clock signal and a second clock signal includes a timer circuit, circuitry for generating a selectively delayed transition of the second clock signal, and phase determination circuitry. The timer circuit produces an elapsed time between a transition of the first clock signal and the selectively delayed transition of the second clock signal. The circuitry for generating the selectively delayed transition of the second clock signal generates the selectively delayed transition in response to a random selection of a respective output from a plurality of second clock signal delay stages. The phase determination circuitry provides the phase difference in response to the elapsed time and the random selection of a respective output from a plurality of second clock signal delay stages.

Abstract: A technique of separating a sequence of modulation shift keying (MSK) symbols into a first portion and a second portion and separately comparing the first portion of the sequence of MSK symbols and the second portion of the sequence of MSK symbols against a first portion of a reference sequence of MSK symbols and a second portion of the reference sequence of MSK symbols allows a low complexity detection of a start field delimiter in a wireless communication packet.

Abstract: Electronic devices and methods to provide wireless ranging are shown. A first electronic device includes a memory containing stored instructions that can perform a method for determining a distance between the first electronic device and a second electronic device. For each frequency in a selected set of frequencies, the method sets the transceiver to the respective frequency, sends a first tone having the frequency and a first phase to the second electronic device and receives a second tone having the first frequency and a second phase. For each selected frequency, the first electronic device determines the phase difference between the second tone and the controllable oscillator, receives a phase difference from the second electronic device, and calculates a phase delay for the frequency. The first electronic device calculates a phase delay difference for pairs of the frequencies; and determines the distance using these phase delay differences.

Abstract: Electronic devices and methods to provide wireless ranging are shown. A first electronic device includes a memory containing stored instructions that can perform a method for determining a distance between the first electronic device and a second electronic device. For each frequency in a selected set of frequencies, the method sets the transceiver to the respective frequency, sends a first tone having the frequency and a first phase to the second electronic device and receives a second tone having the first frequency and a second phase. For each selected frequency, the first electronic device determines the phase difference between the second tone and the controllable oscillator, receives a phase difference from the second electronic device, and calculates a phase delay for the frequency. The first electronic device calculates a phase delay difference for pairs of the frequencies; and determines the distance using these phase delay differences.

Abstract: In described examples, an electronic circuit for determining a phase difference between a first clock signal and a second clock signal includes a timer circuit, circuitry for generating a selectively delayed transition of the second clock signal, and phase determination circuitry. The timer circuit produces an elapsed time between a transition of the first clock signal and the selectively delayed transition of the second clock signal. The circuitry for generating the selectively delayed transition of the second clock signal generates the selectively delayed transition in response to a random selection of a respective output from a plurality of second clock signal delay stages. The phase determination circuitry provides the phase difference in response to the elapsed time and the random selection of a respective output from a plurality of second clock signal delay stages.

Abstract: A technique of separating a sequence of modulation shift keying (MSK) symbols into a first portion and a second portion and separately comparing the first portion of the sequence of MSK symbols and the second portion of the sequence of MSK symbols against a first portion of a reference sequence of MSK symbols and a second portion of the reference sequence of MSK symbols allows a low complexity detection of a start field delimiter in a wireless communication packet.