Patents by Inventor Mariusz Dolny

Mariusz Dolny has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Methods and systems for software based prefetching for low buffer depth sequential read traffic
    Patent number: 12189986
    Abstract: A system and related method, including storage circuitry and a control circuitry, which while executing a storage device driver, is to receive at least one instruction of a stream of instructions for the storage device. The control circuitry determines that a hardware buffer of the storage device is storing less than two instructions. In response to the determination that the hardware buffer of the storage device is storing less than two instructions, the control circuitry accesses data associated with an address of the memory of the storage device, wherein the address is predicted based on analysis of the stream of instructions and causes to be stored the data in a buffer of a plurality of buffers. The control circuitry executes an instruction of the stream of instructions using at least the data stored in the buffer.
    Type: Grant
    Filed: February 12, 2024
    Date of Patent: January 7, 2025
    Assignee: SK Hynix NAND Product Solutions Corp.
    Inventors: Arun Athreya, Mariusz Dolny, Bartosz Kot, Michał Mamczyński, Shivashekar Muralishankar, Shankar Natarajan, Yihua Zhang
  • Methods and systems for software based prefetching for low buffer depth sequential read traffic
    Patent number: 12067284
    Abstract: A system and related method, including storage circuitry and a control circuitry, which while executing a storage device driver, is to receive at least one instruction of a stream of instructions for the storage device. The control circuitry determines that a hardware buffer of the storage device is storing less than two instructions. In response to the determination that the hardware buffer of the storage device is storing less than two instructions, the control circuitry accesses data associated with an address of the memory of the storage device, wherein the address is predicted based on analysis of the stream of instructions and causes to be stored the data in a buffer of a plurality of buffers. The control circuitry executes an instruction of the stream of instructions using at least the data stored in the buffer.
    Type: Grant
    Filed: December 29, 2022
    Date of Patent: August 20, 2024
    Assignee: SK Hynix NAND Product Solutions Corp.
    Inventors: Arun Athreya, Mariusz Dolny, Bartosz Kot, Michal Mamczyński, Shivashekar Muralishankar, Shankar Natarajan, Yihua Zhang
  • METHODS AND SYSTEMS FOR SOFTWARE BASED PREFETCHING FOR LOW BUFFER DEPTH SEQUENTIAL READ TRAFFIC
    Publication number: 20240220156
    Abstract: A system and related method, including storage circuitry and a control circuitry, which while executing a storage device driver, is to receive at least one instruction of a stream of instructions for the storage device. The control circuitry determines that a hardware buffer of the storage device is storing less than two instructions. In response to the determination that the hardware buffer of the storage device is storing less than two instructions, the control circuitry accesses data associated with an address of the memory of the storage device, wherein the address is predicted based on analysis of the stream of instructions and causes to be stored the data in a buffer of a plurality of buffers. The control circuitry executes an instruction of the stream of instructions using at least the data stored in the buffer.
    Type: Application
    Filed: December 29, 2022
    Publication date: July 4, 2024
    Inventors: Arun Athreya, Mariusz Dolny, Bartosz Kot, Michal Mamczynski, Shivashekar Muralishankar, Shankar Natarajan, Yihua Zhang
  • METHODS AND SYSTEMS FOR SOFTWARE BASED PREFETCHING FOR LOW BUFFER DEPTH SEQUENTIAL READ TRAFFIC
    Publication number: 20240220157
    Abstract: A system and related method, including storage circuitry and a control circuitry, which while executing a storage device driver, is to receive at least one instruction of a stream of instructions for the storage device. The control circuitry determines that a hardware buffer of the storage device is storing less than two instructions. In response to the determination that the hardware buffer of the storage device is storing less than two instructions, the control circuitry accesses data associated with an address of the memory of the storage device, wherein the address is predicted based on analysis of the stream of instructions and causes to be stored the data in a buffer of a plurality of buffers. The control circuitry executes an instruction of the stream of instructions using at least the data stored in the buffer.
    Type: Application
    Filed: February 12, 2024
    Publication date: July 4, 2024
    Inventors: Arun Athreya, Mariusz Dolny, Bartosz Kot, Michal Mamczynski, Shivashekar Muralishankar, Shankar Natarajan, Yihua Zhang