Patents by Inventor Mariusz Niewczas

Mariusz Niewczas has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Methods and systems to classify features in electronic designs
    Patent number: 11263496
    Abstract: Methods for matching features in patterns for electronic designs include inputting a set of pattern data for semiconductor or flat panel displays, where the set of pattern data comprises a plurality of features. Each feature in the plurality of features is classified, where the classifying is based on a geometrical context defined by shapes in a region. The classifying uses machine learning techniques.
    Type: Grant
    Filed: February 18, 2020
    Date of Patent: March 1, 2022
    Assignee: D2S, Inc.
    Inventors: Mariusz Niewczas, Abhishek Shendre
  • METHODS AND SYSTEMS TO CLASSIFY FEATURES IN ELECTRONIC DESIGNS
    Publication number: 20200272865
    Abstract: Methods for matching features in patterns for electronic designs include inputting a set of pattern data for semiconductor or flat panel displays, where the set of pattern data comprises a plurality of features. Each feature in the plurality of features is classified, where the classifying is based on a geometrical context defined by shapes in a region. The classifying uses machine learning techniques.
    Type: Application
    Filed: February 18, 2020
    Publication date: August 27, 2020
    Applicant: D2S, Inc.
    Inventors: Mariusz Niewczas, Abhishek Shendre
  • Vertex based layout pattern (VEP): a method and apparatus for describing repetitive patterns in IC mask layout
    Patent number: 6892367
    Abstract: A method to describe a circuit pattern comprises identifying vertices and those edges of the circuit pattern that are not incident with any vertex contained within a region of interest within the circuit pattern. The region of interest includes a portion of a polygon that is less than the entire polygon. The vertices and edges of the circuit pattern are compared to a predetermined set of known vertices and edges. A match may be used to identify an acceptable circuit or a defective circuit.
    Type: Grant
    Filed: June 28, 2002
    Date of Patent: May 10, 2005
    Assignee: PDF Solutions, Inc.
    Inventors: Michal Palusinski, Mariusz Niewczas, Wojciech Maly, Andrezej Strojwas, Thomas Waas, Hans Eisenmann
  • Vertex based layout pattern (VEP): a method and apparatus for describing repetitive patterns in IC mask layout
    Publication number: 20040003357
    Abstract: A method to describe a circuit pattern comprises identifying vertices and those edges of the circuit pattern that are not incident with any vertex contained within a region of interest within the circuit pattern. The region of interest includes a portion of a polygon that is less than the entire polygon. The vertices and edges of the circuit pattern are compared to a predetermined set of known vertices and edges. A match may be used to identify an acceptable circuit or a defective circuit.
    Type: Application
    Filed: June 28, 2002
    Publication date: January 1, 2004
    Inventors: Michal Palusinski, Mariusz Niewczas, Wojciech Maly, Andrezej Stojwas, Thomas Waas, Hans Eisenmann