Abstract: An apparatus and method for secure platform monitoring. For example, one embodiment of a processor comprises: a plurality of processing cores to execute instructions in different execution contexts, including a trusted execution context associated with a trusted execution environment; telemetry aggregation circuitry to aggregate telemetry data associated with one or more of the different execution contexts; a filter to prevent telemetry data associated with the trusted execution context from being aggregated by the telemetry aggregator; and an interface to communicate the telemetry data aggregated by the telemetry aggregation circuitry to an external agent.

Abstract: Examples described herein relate to at least one processor that is to communicate with a management controller to communicate with multiple interfaces. In some examples, wherein at least two of the multiple interfaces are to provide boot firmware code to the at least one processor and a connection interface.

Abstract: A system can predict memory device failure through identification of correctable error patterns based on the memory architecture. The failure prediction can thus account for the circuit-level of the memory rather than the mere number or frequency of correctable errors. A failure prediction engine correlates hardware configuration of the memory device with correctable errors (CEs) detected in data of the memory device to predict an uncorrectable error (UE) based on the correlation.

Abstract: An apparatus and method are described for staging and activating microcode of a processor. For example, one embodiment of a processor comprises: a plurality of functional blocks, each functional block operable, at least in part, based on microcode and including a non-volatile memory to store a corresponding microcode update (MCU); a plurality of MCU staging memories, each MCU staging memory to temporarily store one or more of the MCUs for one or more corresponding functional blocks of the plurality of functional blocks; authentication hardware logic to attempt to validate each MCU of the one or more MCUs stored in each MCU staging memory, wherein each MCU is to be copied to a non-volatile memory of a corresponding functional block only after a successful authentication.

Abstract: A management control message is received to be routed from a first device to a second device in a system. The management control message is determined to include management control data. It is determined whether the second device supports such management control messages and it is determined whether to forward the management control message to the second device based on whether the second device supports management control messages. Management control messages are routed to destination devices within the system over a bridge device associated with the management control messages.

Abstract: Examples described herein relate to at least one multi-core processor and a circuitry can determine and output energy usage of a process regardless of a core of the at least one multi-core processor that executes the process. The circuitry can determine the energy usage of the process based on cache operations and processor microoperations associated with the process. The energy usage of the process can be based on dynamic capacitance (Cdyn) levels and one or more of: temperature of the at least one multi-core processor, input voltage temperature to the at least one multi-core processor, and/or frequency of the at least one multi-core processor.

Abstract: Methods, apparatus, systems and articles of manufacture (e.g., physical storage media) to implement software defined silicon feature licensing are disclosed. Example licensor systems disclosed herein includes a third party verifier to verify one or more credentials included in a request to become an authorized delegated licensor, the request received from a third party. Disclosed example licensor systems also include a feature identifier to identify a feature of a silicon structure which the third party is to be granted the authority to license.

Abstract: A system (204) can respond to detection of an uncorrectable error (UE) (254) in memory (246) based on fault-aware analysis. The fault-aware analysis enables the system (204) to generate a determination of a specific hardware element of the memory (246) that caused the detected UE (254). In response to detection of a UE (254), the system (204) can correlate a hardware configuration (256) of the memory (246) device with historical data indicating memory (246) faults for hardware elements of the hardware configuration (256). Based on a determination of the specific component that likely caused the UE (254), the system (204) can issue a corrective action for the specific hardware element based on the determination.

Abstract: Methods and apparatus for scalable MCTP infrastructure. A system is split into independent MCTP domains, wherein each MCTP domain uses Endpoint Identifiers (EIDs) for endpoint devices within the MCTP domain in a manner similar to conventional MCTP operations. A new class of MCTP devices (referred to as a Domain Controllers) is provided to enable inter-domain communication and communication with global devices. Global traffic originators or receivers like a BMC (Baseboard Management Controller), Infrastructure Processing Unit (IPU), Smart NIC (Network Interface Card), Debugger, or PROT (Platform Root or Trust) discover and establish two-way communication through the Domain Controllers to any of the devices in the target domain(s). The Domain Controllers are configured to implement tunneled connections between global devices and domain endpoint devices.

Abstract: Methods, apparatus, systems and articles of manufacture (e.g., physical storage media) to implement license management solutions for software defined silicon (SDSi) products are disclosed. Example license management solutions disclosed herein include, but are not limited to, virtual resource migration using SDSi, resource configuration management using SDSi, hardware self-configuration using SDSi, reduced footprint agents using SDSi, performing SDSi usage evaluation and corresponding license transfer responsive to detected and/or predicted failures, transferring node locked SDSi licenses, transfer of SDSi licenses without a trusted license server, community license generation, expirable SDSi licenses via a reliable clock, non-node locked licenses via blockchain, and activating hardware features with a pre-generated hardware license.

Abstract: Methods, apparatus, systems and articles of manufacture (e.g., physical storage media) to implement software defined silicon feature configuration pay-as-you-go licensing are disclosed. A disclosed silicon semiconductor device includes a first counter that increments a first count when a timer expires and, responsive to expiration of the timer, a feature configuration sampler to sample a state of a configuration of a feature of the silicon semiconductor device. In addition, the silicon semiconductor device includes a second counter that increments a second count when the sampled state of the configuration of the feature indicates the feature is active. A feature up-time tracker is also included outputs a value representative of an amount of time the configuration has been active, where the amount of time is based on the first count and the second count.

Abstract: A system can predict memory device failure through identification of correctable error patterns based on the memory architecture. The failure prediction can thus account for the circuit-level of the memory rather than the mere number or frequency of correctable errors. A failure prediction engine correlates hardware configuration of the memory device with correctable errors (CEs) detected in data of the memory device to predict an uncorrectable error (UE) based on the correlation.

Abstract: Methods, apparatus, systems and articles of manufacture (e.g., physical storage media) to implement and manage software defined silicon products are disclosed. Example semiconductor devices disclosed herein include circuitry configurable to provide one or more features. Disclosed example semiconductor devices also include a license processor to activate or deactivate at least one of the one or more features based on a license received via a network from a first remote enterprise system. Disclosed example semiconductor devices further include an analytics engine to report telemetry data associated with operation of the semiconductor device to at least one of the first remote enterprise system or a second remote enterprise system, the analytics engine to report the telemetry data in response to activation or deactivation of the at least one of the one or more features based on the license.

Abstract: Methods and apparatus for scalable MCTP infrastructure. A system is split into independent MCTP domains, wherein each MCTP domain uses Endpoint Identifiers (EIDs) for endpoint devices within the MCTP domain in a manner similar to conventional MCTP operations. A new class of MCTP devices (referred to as a Domain Controllers) is provided to enable inter-domain communication and communication with global devices. Global traffic originators or receivers like a BMC (Baseboard Management Controller), Infrastructure Processing Unit (IPU), Smart NIC (Network Interface Card), Debugger, or PROT (Platform Root or Trust) discover and establish two-way communication through the Domain Controllers to any of the devices in the target domain(s). The Domain Controllers are configured to implement tunneled connections between global devices and domain endpoint devices.

Abstract: Methods, apparatus, systems and articles of manufacture (e.g., physical storage media) to implement and manage software defined silicon products are disclosed. Example semiconductor devices disclosed herein include circuitry configurable to provide one or more features. Disclosed example semiconductor devices also include a license processor to activate or deactivate at least one of the one or more features based on a license received via a network from a first remote enterprise system. Disclosed example semiconductor devices further include an analytics engine to report telemetry data associated with operation of the semiconductor device to at least one of the first remote enterprise system or a second remote enterprise system, the analytics engine to report the telemetry data in response to activation or deactivation of the at least one of the one or more features based on the license.

Abstract: Methods and apparatus for lifetime telemetry on memory error statistics to improve memory failure analysis and prevention. Memory error information corresponding to detected correctable errors and uncorrectable memory errors are monitored, with the memory error information identifying an associated DRAM device in an associated DIMM. Corresponding micro-level error bits information from the memory error information is decoded and Micro-level Error Statistic Indicators (MESIs) are generated. Information associated with the MESIs from DRAM devices on the DIMMs are periodically written to persistent storage on those DIMMs. The MESIs for a given DIMM are updated over the lifetime of the DIMM.

Abstract: Methods, apparatus, systems and articles of manufacture (e.g., physical storage media) to implement software defined silicon feature licensing are disclosed. Example licensor systems disclosed herein includes a third party verifier to verify one or more credentials included in a request to become an authorized delegated licensor, the request received from a third party. Disclosed example licensor systems also include a feature identifier to identify a feature of a silicon structure which the third party is to be granted the authority to license.

Abstract: Techniques and apparatus for managing a distributed computing environment using event digests are described. In one embodiment, for example, an apparatus may include at least one memory, and logic for a system manager, at least a portion of the logic comprised in hardware coupled to the at least one memory, the logic to determine a workload to schedule, access an event digest associated with a plurality of compute hosts, the event digest comprising event digest values determined using out-of-band information, determine metrics from the event digest, generate at least one host weight for at least a portion of the plurality of compute hosts based on the metrics, identify at least one candidate host from the portion of the plurality of compute hosts based on the at least one host weight, and schedule the workload on the at least one candidate host. Other embodiments are described and claimed.

Abstract: An apparatus is provided which comprises: a first circuitry to receive a measurement of a first temperature of a section of a computing device during a first loading condition of the computing device, and to receive a measurement of a second temperature of the section of the computing device during a second loading condition of the computing device; and a second circuitry to detect a potential fault in a cooling system to cool the computing device, based at least in part on the first temperature and the second temperature.

Abstract: A method and apparatus for coordinating and authenticating requests for data. In one embodiment, the apparatus comprises: a baseboard management controller (BMC); and a request coordinator coupled to the BMC to intercept BMC requests and to provide intercepted requests to the BMC, where the coordination interface comprises a request parser to parse parameters for each of the BMC requests, one or more queues to store the requests while the BMC is servicing another BMC request, and a command submitter to send individual BMC requests to the BMC, wherein the BMC is operable to generate the responses to the BMC requests received from the coordination interface and to send the responses to the coordination interface.