Patents by Inventor Mariusz Oriol
Mariusz Oriol has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11960439Abstract: Methods and apparatus for scalable MCTP infrastructure. A system is split into independent MCTP domains, wherein each MCTP domain uses Endpoint Identifiers (EIDs) for endpoint devices within the MCTP domain in a manner similar to conventional MCTP operations. A new class of MCTP devices (referred to as a Domain Controllers) is provided to enable inter-domain communication and communication with global devices. Global traffic originators or receivers like a BMC (Baseboard Management Controller), Infrastructure Processing Unit (IPU), Smart NIC (Network Interface Card), Debugger, or PROT (Platform Root or Trust) discover and establish two-way communication through the Domain Controllers to any of the devices in the target domain(s). The Domain Controllers are configured to implement tunneled connections between global devices and domain endpoint devices.Type: GrantFiled: March 9, 2022Date of Patent: April 16, 2024Assignee: Intel CorporationInventors: Janusz Jurski, Myron Loewen, Mariusz Oriol, Patrick Schoeller, Jerry Backer, Richard Marian Thomaiyar, Eliel Louzoun, Piotr Matuszczak
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Publication number: 20240095315Abstract: Methods, apparatus, systems and articles of manufacture (e.g., physical storage media) to implement license management solutions for software defined silicon (SDSi) products are disclosed. Example license management solutions disclosed herein include, but are not limited to, virtual resource migration using SDSi, resource configuration management using SDSi, hardware self-configuration using SDSi, reduced footprint agents using SDSi, performing SDSi usage evaluation and corresponding license transfer responsive to detected and/or predicted failures, transferring node locked SDSi licenses, transfer of SDSi licenses without a trusted license server, community license generation, expirable SDSi licenses via a reliable clock, non-node locked licenses via blockchain, and activating hardware features with a pre-generated hardware license.Type: ApplicationFiled: September 25, 2023Publication date: March 21, 2024Inventors: Katalin Bartfai-Walcott, Mariusz Oriol, Vasudevan Srinivasan, Peggy Irelan, Mariusz Stepka, Kaitlin Murphy, Bharat Pillilli, Mark Baldwin, Mateusz Bronk, Fariaz Karim, Arkadiusz Berent, Vasuki Chilukuri
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Publication number: 20240054039Abstract: Methods, apparatus, systems and articles of manufacture (e.g., physical storage media) to implement software defined silicon feature configuration pay-as-you-go licensing are disclosed. A disclosed silicon semiconductor device includes a first counter that increments a first count when a timer expires and, responsive to expiration of the timer, a feature configuration sampler to sample a state of a configuration of a feature of the silicon semiconductor device. In addition, the silicon semiconductor device includes a second counter that increments a second count when the sampled state of the configuration of the feature indicates the feature is active. A feature up-time tracker is also included outputs a value representative of an amount of time the configuration has been active, where the amount of time is based on the first count and the second count.Type: ApplicationFiled: December 23, 2020Publication date: February 15, 2024Inventors: Vasudevan SRINIVASAN, Knut GRIMSRUD, Johan VAN DE GROENENDAAL, Mariusz ORIOL, Nishi AHUJA, Shen ZHOU, Samantha ALT, Katalin BARTFAI-WALCOTT, Arkadiusz BERENT
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Publication number: 20230083193Abstract: A system can predict memory device failure through identification of correctable error patterns based on the memory architecture. The failure prediction can thus account for the circuit-level of the memory rather than the mere number or frequency of correctable errors. A failure prediction engine correlates hardware configuration of the memory device with correctable errors (CEs) detected in data of the memory device to predict an uncorrectable error (UE) based on the correlation.Type: ApplicationFiled: June 15, 2021Publication date: March 16, 2023Inventors: Shen ZHOU, Xiaoming DU, Cong LI, Kuljit S. BAINS, Rajat AGARWAL, Murugasamy K. NACHIMUTHU, Maciej LAWNICZAK, Chao Yan TANG, Mariusz ORIOL
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Patent number: 11573830Abstract: Methods, apparatus, systems and articles of manufacture (e.g., physical storage media) to implement and manage software defined silicon products are disclosed. Example semiconductor devices disclosed herein include circuitry configurable to provide one or more features. Disclosed example semiconductor devices also include a license processor to activate or deactivate at least one of the one or more features based on a license received via a network from a first remote enterprise system. Disclosed example semiconductor devices further include an analytics engine to report telemetry data associated with operation of the semiconductor device to at least one of the first remote enterprise system or a second remote enterprise system, the analytics engine to report the telemetry data in response to activation or deactivation of the at least one of the one or more features based on the license.Type: GrantFiled: September 25, 2020Date of Patent: February 7, 2023Assignee: Intel CorporationInventors: Katalin Klara Bartfai-Walcott, Arkadiusz Berent, Vasuki Chilukuri, Mark Baldwin, Vasudevan Srinivasan, Vinila Rose, Mariusz Oriol, Justyna Chilczuk, Bartosz Gotowalski
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Publication number: 20220197859Abstract: Methods and apparatus for scalable MCTP infrastructure. A system is split into independent MCTP domains, wherein each MCTP domain uses Endpoint Identifiers (EIDs) for endpoint devices within the MCTP domain in a manner similar to conventional MCTP operations. A new class of MCTP devices (referred to as a Domain Controllers) is provided to enable inter-domain communication and communication with global devices. Global traffic originators or receivers like a BMC (Baseboard Management Controller), Infrastructure Processing Unit (IPU), Smart NIC (Network Interface Card), Debugger, or PROT (Platform Root or Trust) discover and establish two-way communication through the Domain Controllers to any of the devices in the target domain(s). The Domain Controllers are configured to implement tunneled connections between global devices and domain endpoint devices.Type: ApplicationFiled: March 9, 2022Publication date: June 23, 2022Inventors: Janusz JURSKI, Myron LOEWEN, Mariusz ORIOL, Patrick SCHOELLER, Jerry BACKER, Richard Marian THOMAIYAR, Eliel LOUZOUN, Piotr MATUSZCZAK
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Publication number: 20220092154Abstract: Methods, apparatus, systems and articles of manufacture (e.g., physical storage media) to implement and manage software defined silicon products are disclosed. Example semiconductor devices disclosed herein include circuitry configurable to provide one or more features. Disclosed example semiconductor devices also include a license processor to activate or deactivate at least one of the one or more features based on a license received via a network from a first remote enterprise system. Disclosed example semiconductor devices further include an analytics engine to report telemetry data associated with operation of the semiconductor device to at least one of the first remote enterprise system or a second remote enterprise system, the analytics engine to report the telemetry data in response to activation or deactivation of the at least one of the one or more features based on the license.Type: ApplicationFiled: September 25, 2020Publication date: March 24, 2022Inventors: Katalin Klara Bartfai-Walcott, Arkadiusz Berent, Vasuki Chilukuri, Mark Baldwin, Vasudevan Srinivasan, Vinila Rose, Mariusz Oriol, Justyna Chilczuk, Bartosz Gotowalski
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Publication number: 20210279122Abstract: Methods and apparatus for lifetime telemetry on memory error statistics to improve memory failure analysis and prevention. Memory error information corresponding to detected correctable errors and uncorrectable memory errors are monitored, with the memory error information identifying an associated DRAM device in an associated DIMM. Corresponding micro-level error bits information from the memory error information is decoded and Micro-level Error Statistic Indicators (MESIs) are generated. Information associated with the MESIs from DRAM devices on the DIMMs are periodically written to persistent storage on those DIMMs. The MESIs for a given DIMM are updated over the lifetime of the DIMM.Type: ApplicationFiled: May 11, 2021Publication date: September 9, 2021Inventors: Shen ZHOU, Cong LI, Kuljit S. BAINS, Xiaoming DU, Mariusz ORIOL
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Publication number: 20210012445Abstract: Methods, apparatus, systems and articles of manufacture (e.g., physical storage media) to implement software defined silicon feature licensing are disclosed. Example licensor systems disclosed herein includes a third party verifier to verify one or more credentials included in a request to become an authorized delegated licensor, the request received from a third party. Disclosed example licensor systems also include a feature identifier to identify a feature of a silicon structure which the third party is to be granted the authority to license.Type: ApplicationFiled: September 25, 2020Publication date: January 14, 2021Inventors: Katalin Klara Bartfai-Walcott, Mark Baldwin, Arkadiusz Berent, Bartosz Gotowalski, Vasuki Chilukuri, Vasudevan Srinivasan, Justyna Chilczuk, Vinila Rose, Mariusz Oriol
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Patent number: 10747640Abstract: Techniques and apparatus for managing a distributed computing environment using event digests are described. In one embodiment, for example, an apparatus may include at least one memory, and logic for a system manager, at least a portion of the logic comprised in hardware coupled to the at least one memory, the logic to determine a workload to schedule, access an event digest associated with a plurality of compute hosts, the event digest comprising event digest values determined using out-of-band information, determine metrics from the event digest, generate at least one host weight for at least a portion of the plurality of compute hosts based on the metrics, identify at least one candidate host from the portion of the plurality of compute hosts based on the at least one host weight, and schedule the workload on the at least one candidate host. Other embodiments are described and claimed.Type: GrantFiled: June 28, 2017Date of Patent: August 18, 2020Assignee: INTEL CORPORATIONInventors: Ananth S. Narayan, Lukasz Grzymkowski, Mrittika Ganguli, Mariusz Oriol
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Patent number: 10612980Abstract: An apparatus is provided which comprises: a first circuitry to receive a measurement of a first temperature of a section of a computing device during a first loading condition of the computing device, and to receive a measurement of a second temperature of the section of the computing device during a second loading condition of the computing device; and a second circuitry to detect a potential fault in a cooling system to cool the computing device, based at least in part on the first temperature and the second temperature.Type: GrantFiled: June 21, 2017Date of Patent: April 7, 2020Assignee: Intel CorporationInventors: Janusz P. Jurski, Tozer J. Bandorawalla, Ramkumar Nagappan, Mariusz Oriol, Piotr Sawicki, Robin A. Steinbrecher, Shankar Krishnan
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Patent number: 10404676Abstract: A method and apparatus for coordinating and authenticating requests for data. In one embodiment, the apparatus comprises: a baseboard management controller (BMC); and a request coordinator coupled to the BMC to intercept BMC requests and to provide intercepted requests to the BMC, where the coordination interface comprises a request parser to parse parameters for each of the BMC requests, one or more queues to store the requests while the BMC is servicing another BMC request, and a command submitter to send individual BMC requests to the BMC, wherein the BMC is operable to generate the responses to the BMC requests received from the coordination interface and to send the responses to the coordination interface.Type: GrantFiled: March 29, 2016Date of Patent: September 3, 2019Assignee: INTEL CORPORATIONInventors: Justin J. Song, Devadatta V. Bodas, Muralidhar Rajappa, Andy Hoffman, Mariusz Oriol, Gopal R. Mundada
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Publication number: 20180372551Abstract: An apparatus is provided which comprises: a first circuitry to receive a measurement of a first temperature of a section of a computing device during a first loading condition of the computing device, and to receive a measurement of a second temperature of the section of the computing device during a second loading condition of the computing device; and a second circuitry to detect a potential fault in a cooling system to cool the computing device, based at least in part on the first temperature and the second temperature.Type: ApplicationFiled: June 21, 2017Publication date: December 27, 2018Inventors: Janusz P. Jurski, Tozer J. Bandorawalla, Ramkumar Nagappan, Mariusz Oriol, Piotr Sawicki, Robin A. Steinbrecher, Shankar Krishnan
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Patent number: 10073742Abstract: Technologies for providing manageability redundancy for micro server and clustered System-on-a-Chip (SoC) deployments are presented. A configurable multi-processor apparatus may include multiple integrated circuit (IC) blocks where each IC block includes a task block to perform one or more assignable task functions and a management block to perform management functions with respect to the corresponding IC block. Each task block and each management block may include one or more instruction processors and corresponding memory. Each IC block may be controllable to perform a function of one or more other IC blocks. The IC blocks may communicate with each other via a management communication infrastructure that may include a communication path from each of the management blocks to each of the other management blocks. Via the management communication infrastructure, the management blocks may bridge communication paths between pairs of management blocks.Type: GrantFiled: June 9, 2016Date of Patent: September 11, 2018Assignee: Intel CorporationInventors: Robert C. Swanson, Mariusz Oriol, Janusz Jurski, Piotr Sawicki, Robert W. Cone, William J. O'Sullivan, Mariusz Stepka, Babak Nikjou, Madhusudhan Rangarajan, Pawel Szymanski, Piotr Kwidzinski, Robert Bahnsen, Mallik Bulusu
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Publication number: 20180129503Abstract: Techniques and apparatus for managing a distributed computing environment using event digests are described. In one embodiment, for example, an apparatus may include at least one memory, and logic for a system manager, at least a portion of the logic comprised in hardware coupled to the at least one memory, the logic to determine a workload to schedule, access an event digest associated with a plurality of compute hosts, the event digest comprising event digest values determined using out-of-band information, determine metrics from the event digest, generate at least one host weight for at least a portion of the plurality of compute hosts based on the metrics, identify at least one candidate host from the portion of the plurality of compute hosts based on the at least one host weight, and schedule the workload on the at least one candidate host. Other embodiments are described and claimed.Type: ApplicationFiled: June 28, 2017Publication date: May 10, 2018Applicant: INTEL CORPORATIONInventors: ANANTH S. NARAYAN, LUKASZ GRZYMKOWSKI, MRITTIKA GANGULI, MARIUSZ ORIOL
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Patent number: 9891686Abstract: An apparatus and system for throttling I/O devices in a computer system is provided. In an example, a method for throttling device power demand during critical power events. The method includes detecting a critical power event and issuing a signal to system devices to defer optional transactions during the critical power event.Type: GrantFiled: September 26, 2013Date of Patent: February 13, 2018Assignee: Intel CorporationInventors: Janusz Jurski, Robert Swanson, Anil Kumar, Mariusz Oriol, Waldemar Piotrewicz
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Publication number: 20170289300Abstract: A method and apparatus for coordinating and authenticating requests for data. In one embodiment, the apparatus comprises: a baseboard management controller (BMC); and a request coordinator coupled to the BMC to intercept BMC requests and to provide intercepted requests to the BMC, where the coordination interface comprises a request parser to parse parameters for each of the BMC requests, one or more queues to store the requests while the BMC is servicing another BMC request, and a command submitter to send individual BMC requests to the BMC, wherein the BMC is operable to generate the responses to the BMC requests received from the coordination interface and to send the responses to the coordination interface.Type: ApplicationFiled: March 29, 2016Publication date: October 5, 2017Inventors: Justin J. Song, Devadatta V. Bodas, Muralidhar Rajappa, Andy Hoffman, Mariusz Oriol, Gopal Mundada
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Patent number: 9547497Abstract: Technologies for facilitating inter-system-on-a-chip (SoC) communication include a first SoC, a second SoC, and a dedicated manageability controller network. The first SoC includes a first main processor, a first manageability controller, and a memory dedicated to the first manageability controller and having manageability controller firmware stored thereon. The first manageability controller is different from the first main processor and to control functions of the first SoC. The second SoC is different from the first SoC and includes a second main processor and a second manageability control, which is different from the second main processor and to control functions of the second SoC. The second SoC is to access the manageability controller firmware of the memory of the first SoC over the dedicated manageability network.Type: GrantFiled: September 27, 2013Date of Patent: January 17, 2017Assignee: Intel CorporationInventors: Robert C. Swanson, Robert W. Cone, William J. O'Sullivan, Mariusz Oriol, Pawel Szymanski, Babak Nikjou, Madhusudhan Rangarajan, Janusz Jurski, Piotr Kwidzinski, Mariusz Stepka, Piotr Sawicki
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Publication number: 20160292038Abstract: Technologies for providing manageability redundancy for micro server and clustered System-on-a-Chip (SoC) deployments are presented. A configurable multi-processor apparatus may include multiple integrated circuit (IC) blocks where each IC block includes a task block to perform one or more assignable task functions and a management block to perform management functions with respect to the corresponding IC block. Each task block and each management block may include one or more instruction processors and corresponding memory. Each IC block may be controllable to perform a function of one or more other IC blocks. The IC blocks may communicate with each other via a management communication infrastructure that may include a communication path from each of the management blocks to each of the other management blocks. Via the management communication infrastructure, the management blocks may bridge communication paths between pairs of management blocks.Type: ApplicationFiled: June 9, 2016Publication date: October 6, 2016Inventors: Robert C. Swanson, Mariusz Oriol, Janusz Jurski, Piotr Sawicki, Robert W. Cone, William J. O'Sullivan, Mariusz Stepka, Babak Nikjou, Madhusudhan Rangarajan, Pawel Szymanski, Piotr Kwidzinski, Robert Bahnsen, Mallik Bulusu
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Publication number: 20160202994Abstract: Technologies for facilitating inter-system-on-a-chip (SoC) communication include a first SoC, a second SoC, and a dedicated manageability controller network. The first SoC includes a first main processor, a first manageability controller, and a memory dedicated to the first manageability controller and having manageability controller firmware stored thereon. The first manageability controller is different from the first main processor and to control functions of the first SoC. The second SoC is different from the first SoC and includes a second main processor and a second manageability control, which is different from the second main processor and to control functions of the second SoC. The second SoC is to access the manageability controller firmware of the memory of the first SoC over the dedicated manageability network.Type: ApplicationFiled: September 27, 2013Publication date: July 14, 2016Inventors: Robert C. SWANSON, Robert W. CONE, William J. O'SULLIVAN, Mariusz ORIOL, Pawel SZYMANSKI, BABAK NIKJOU, Madhusudhan RANGARAJAN, Janusz JURSKI, Piotr KWIDZINSKI, Mariusz STEPKA, Piotr SAWICKI