Patents by Inventor Mariusz Stepka
Mariusz Stepka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240095315Abstract: Methods, apparatus, systems and articles of manufacture (e.g., physical storage media) to implement license management solutions for software defined silicon (SDSi) products are disclosed. Example license management solutions disclosed herein include, but are not limited to, virtual resource migration using SDSi, resource configuration management using SDSi, hardware self-configuration using SDSi, reduced footprint agents using SDSi, performing SDSi usage evaluation and corresponding license transfer responsive to detected and/or predicted failures, transferring node locked SDSi licenses, transfer of SDSi licenses without a trusted license server, community license generation, expirable SDSi licenses via a reliable clock, non-node locked licenses via blockchain, and activating hardware features with a pre-generated hardware license.Type: ApplicationFiled: September 25, 2023Publication date: March 21, 2024Inventors: Katalin Bartfai-Walcott, Mariusz Oriol, Vasudevan Srinivasan, Peggy Irelan, Mariusz Stepka, Kaitlin Murphy, Bharat Pillilli, Mark Baldwin, Mateusz Bronk, Fariaz Karim, Arkadiusz Berent, Vasuki Chilukuri
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Patent number: 11544129Abstract: Systems, apparatuses and methods may provide for technology that detects a successful boot of a first firmware component in a computing system, receives a signal from a second firmware component in the computing system, and detects an incompatibility of the first firmware component with respect to the second firmware component based on the signal. In one example, only the first firmware component is repaired in response to the incompatibility.Type: GrantFiled: September 3, 2021Date of Patent: January 3, 2023Assignee: Intel CorporationInventors: Janusz Jurski, Mariusz Stepka
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Publication number: 20210397507Abstract: Systems, apparatuses and methods may provide for technology that detects a successful boot of a first firmware component in a computing system, receives a signal from a second firmware component in the computing system, and detects an incompatibility of the first firmware component with respect to the second firmware component based on the signal. In one example, only the first firmware component is repaired in response to the incompatibility.Type: ApplicationFiled: September 3, 2021Publication date: December 23, 2021Applicant: Intel CorporationInventors: Janusz Jurski, Mariusz Stepka
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Patent number: 11113133Abstract: Systems, apparatuses and methods may provide for technology that detects a successful boot of a first firmware component in a computing system, receives a signal from a second firmware component in the computing system, and detects an incompatibility of the first firmware component with respect to the second firmware component based on the signal. In one example, only the first firmware component is repaired in response to the incompatibility.Type: GrantFiled: December 27, 2016Date of Patent: September 7, 2021Assignee: Intel CorporationInventors: Janusz Jurski, Mariusz Stepka
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Publication number: 20190347153Abstract: Systems, apparatuses and methods may provide for technology that detects a successful boot of a first firmware component in a computing system, receives a signal from a second firmware component in the computing system, and detects an incompatibility of the first firmware component with respect to the second firmware component based on the signal. In one example, only the first firmware component is repaired in response to the incompatibility.Type: ApplicationFiled: December 27, 2016Publication date: November 14, 2019Applicant: Intel CorporationInventors: Janusz JURSKI, Mariusz STEPKA
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Patent number: 10073742Abstract: Technologies for providing manageability redundancy for micro server and clustered System-on-a-Chip (SoC) deployments are presented. A configurable multi-processor apparatus may include multiple integrated circuit (IC) blocks where each IC block includes a task block to perform one or more assignable task functions and a management block to perform management functions with respect to the corresponding IC block. Each task block and each management block may include one or more instruction processors and corresponding memory. Each IC block may be controllable to perform a function of one or more other IC blocks. The IC blocks may communicate with each other via a management communication infrastructure that may include a communication path from each of the management blocks to each of the other management blocks. Via the management communication infrastructure, the management blocks may bridge communication paths between pairs of management blocks.Type: GrantFiled: June 9, 2016Date of Patent: September 11, 2018Assignee: Intel CorporationInventors: Robert C. Swanson, Mariusz Oriol, Janusz Jurski, Piotr Sawicki, Robert W. Cone, William J. O'Sullivan, Mariusz Stepka, Babak Nikjou, Madhusudhan Rangarajan, Pawel Szymanski, Piotr Kwidzinski, Robert Bahnsen, Mallik Bulusu
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Patent number: 9547497Abstract: Technologies for facilitating inter-system-on-a-chip (SoC) communication include a first SoC, a second SoC, and a dedicated manageability controller network. The first SoC includes a first main processor, a first manageability controller, and a memory dedicated to the first manageability controller and having manageability controller firmware stored thereon. The first manageability controller is different from the first main processor and to control functions of the first SoC. The second SoC is different from the first SoC and includes a second main processor and a second manageability control, which is different from the second main processor and to control functions of the second SoC. The second SoC is to access the manageability controller firmware of the memory of the first SoC over the dedicated manageability network.Type: GrantFiled: September 27, 2013Date of Patent: January 17, 2017Assignee: Intel CorporationInventors: Robert C. Swanson, Robert W. Cone, William J. O'Sullivan, Mariusz Oriol, Pawel Szymanski, Babak Nikjou, Madhusudhan Rangarajan, Janusz Jurski, Piotr Kwidzinski, Mariusz Stepka, Piotr Sawicki
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Publication number: 20160292038Abstract: Technologies for providing manageability redundancy for micro server and clustered System-on-a-Chip (SoC) deployments are presented. A configurable multi-processor apparatus may include multiple integrated circuit (IC) blocks where each IC block includes a task block to perform one or more assignable task functions and a management block to perform management functions with respect to the corresponding IC block. Each task block and each management block may include one or more instruction processors and corresponding memory. Each IC block may be controllable to perform a function of one or more other IC blocks. The IC blocks may communicate with each other via a management communication infrastructure that may include a communication path from each of the management blocks to each of the other management blocks. Via the management communication infrastructure, the management blocks may bridge communication paths between pairs of management blocks.Type: ApplicationFiled: June 9, 2016Publication date: October 6, 2016Inventors: Robert C. Swanson, Mariusz Oriol, Janusz Jurski, Piotr Sawicki, Robert W. Cone, William J. O'Sullivan, Mariusz Stepka, Babak Nikjou, Madhusudhan Rangarajan, Pawel Szymanski, Piotr Kwidzinski, Robert Bahnsen, Mallik Bulusu
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Publication number: 20160202994Abstract: Technologies for facilitating inter-system-on-a-chip (SoC) communication include a first SoC, a second SoC, and a dedicated manageability controller network. The first SoC includes a first main processor, a first manageability controller, and a memory dedicated to the first manageability controller and having manageability controller firmware stored thereon. The first manageability controller is different from the first main processor and to control functions of the first SoC. The second SoC is different from the first SoC and includes a second main processor and a second manageability control, which is different from the second main processor and to control functions of the second SoC. The second SoC is to access the manageability controller firmware of the memory of the first SoC over the dedicated manageability network.Type: ApplicationFiled: September 27, 2013Publication date: July 14, 2016Inventors: Robert C. SWANSON, Robert W. CONE, William J. O'SULLIVAN, Mariusz ORIOL, Pawel SZYMANSKI, BABAK NIKJOU, Madhusudhan RANGARAJAN, Janusz JURSKI, Piotr KWIDZINSKI, Mariusz STEPKA, Piotr SAWICKI
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Patent number: 9367406Abstract: Technologies for providing manageability redundancy for micro server and clustered System-on-a-Chip (SoC) deployments are presented. A configurable multi-processor apparatus may include multiple integrated circuit (IC) blocks where each IC block includes a task block to perform one or more assignable task functions and a management block to perform management functions with respect to the corresponding IC block. Each task block and each management block may include one or more instruction processors and corresponding memory. Each IC block may be controllable to perform a function of one or more other IC blocks. The IC blocks may communicate with each other via a management communication infrastructure that may include a communication path from each of the management blocks to each of the other management blocks. Via the management communication infrastructure, the management blocks may bridge communication paths between pairs of management blocks.Type: GrantFiled: August 14, 2013Date of Patent: June 14, 2016Assignee: Intel CorporationInventors: Robert C. Swanson, Mariusz Oriol, Janusz Jurski, Piotr Sawicki, Robert W. Cone, William J. O'Sullivan, Mariusz Stepka, Babak Nikjou, Madhusudhan Rangarajan, Pawel Szymanski, Piotr Kwidzinski, Robert Bahnsen, Mallik Bulusu
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Publication number: 20150052389Abstract: Technologies for providing manageability redundancy for micro server and clustered System-on-a-Chip (SoC) deployments are presented. A configurable multi-processor apparatus may include multiple integrated circuit (IC) blocks where each IC block includes a task block to perform one or more assignable task functions and a management block to perform management functions with respect to the corresponding IC block. Each task block and each management block may include one or more instruction processors and corresponding memory. Each IC block may be controllable to perform a function of one or more other IC blocks. The IC blocks may communicate with each other via a management communication infrastructure that may include a communication path from each of the management blocks to each of the other management blocks. Via the management communication infrastructure, the management blocks may bridge communication paths between pairs of management blocks.Type: ApplicationFiled: August 14, 2013Publication date: February 19, 2015Inventors: Robert C. Swanson, Mariusz Oriol, Janusz Jurski, Piotr Sawicki, Robert W. Cone, William J. O'Sullivan, Mariusz Stepka, Babak Nikjou, Madhusudhan Rangarajan, Pawel Szymanski, Piotr Kwidzinski, Robert Bahnsen, Mallik Bulusu