Patents by Inventor Mark A. Anders

Mark A. Anders has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20180344993
    Abstract: A system for clearing a blockage from a lumen of a patient, such as an impacted food bolus, can include a catheter that includes a distal end for insertion into the lumen of the patient. The catheter further includes a proximal end for coupling with a suction source at a position external to the patient. The catheter further includes a lumen extending through the proximal and distal ends. The system can include a cutting tip for cutting a morsel from the bolus as suction is applied to the bolus via the lumen of the catheter. The system can also include a positioning element that transitions from an undeployed state to a deployed state, which is expanded relative to the undeployed state. The positioning element can contact the esophagus to space the cutting tip from the esophagus when in the deployed state.
    Type: Application
    Filed: May 31, 2018
    Publication date: December 6, 2018
    Inventors: Robert A. Ganz, Mark Anders Rydell, Travis Sessions, Steven Berhow, Doug Wahnschaffe, Michael W. Augustine
  • Publication number: 20180315399
    Abstract: One embodiment provides for a graphics processing unit to accelerate machine-learning operations, the graphics processing unit comprising a multiprocessor having a single instruction, multiple thread (SIMT) architecture, the multiprocessor to execute at least one single instruction; and a first compute unit included within the multiprocessor, the at least one single instruction to cause the first compute unit to perform a two-dimensional matrix multiply and accumulate operation, wherein to perform the two-dimensional matrix multiply and accumulate operation includes to compute a 32-bit intermediate product of 16-bit operands and to compute a 32-bit sum based on the 32-bit intermediate product.
    Type: Application
    Filed: November 21, 2017
    Publication date: November 1, 2018
    Applicant: Intel Corporation
    Inventors: Himanshu Kaul, Mark A. Anders, Sanu K. Mathew, Anbang Yao, Joydeep Ray, Ping T. Tang, Michael S. Strickland, Xiaoming Chen, Tatiana Shpeisman, Abhishek R. Appu, Altug Koker, Kamal Sinha, Balaji Vembu, Nicolas C. Galoppo Von Borries, Eriko Nurvitadhi, Rajkishore Barik, Tsung-Han Lin, Vasanth Ranganathan, Sanjeev Jahagirdar
  • Publication number: 20180315398
    Abstract: One embodiment provides for a machine-learning hardware accelerator comprising a compute unit having an adder and a multiplier that are shared between integer data path and a floating-point datapath, the upper bits of input operands to the multiplier to be gated during floating-point operation.
    Type: Application
    Filed: October 18, 2017
    Publication date: November 1, 2018
    Applicant: Intel Corporation
    Inventors: Himanshu Kaul, Mark A. Anders, Sanu K. Mathew, Anbang Yao, Joydeep Ray, Ping T. Tang, Michael S. Strickland, Xiaoming Chen, Tatiana Shpeisman, Abhishek R. Appu, Altug Koker, Kamal Sinha, Balaji Vembu, Nicolas C. Galoppo Von Borries, Eriko Nurvitadhi, Rajkishore Barik, Tsung-Han Lin, Vasanth Ranganathan, Sanjeev Jahagirdar
  • Publication number: 20180280040
    Abstract: A system for clearing a blockage in a patient can include a tubular member that defines a channel, the tubular member being insertable into an esophagus of the patient. The system can further include a catheter assembly that includes a catheter tube, which defines a length greater than a length of the tubular member and is passable through the channel of the tubular member while the tubular member is positioned in the esophagus of the patient. The catheter tube can include a distal tip that defines a cutting element to core the blockage positioned in the esophagus of the patient. The catheter assembly can further include a proximal end coupled with the catheter tube, the proximal end being couplable with a vacuum line such that, when suction is provided via the vacuum line, advancement of the catheter tube into contact with the blockage cores from the blockage a piece of the blockage that is passed through the catheter.
    Type: Application
    Filed: May 31, 2018
    Publication date: October 4, 2018
    Inventors: Robert A. Ganz, Mark Anders Rydell, Travis Sessions, Steven Berhow, Doug Wahnschaffe, Michael W. Augustine
  • Publication number: 20180167199
    Abstract: An instruction and logic for a Simon-based hashing for validation are described. In one embodiment, a processor comprises: a memory the memory to store a plurality of values; and a hash circuit comprising a Simon cipher circuit operable to receive the plurality of values from the memory, to apply a Simon cipher, and to generate an output for each of the plurality of values; and circuitry coupled to the Simon cipher circuit to combine outputs from the Simon cipher circuit for each value of the plurality of values into a hash digest that is indicative of whether the values in the memory are valid.
    Type: Application
    Filed: December 9, 2016
    Publication date: June 14, 2018
    Inventors: Himanshu Kaul, Sanu K. Mathew, Mark A. Anders, Jesse Walker, Jason G. Sandri
  • Patent number: 9992042
    Abstract: A packet-switched request from a first router of a network-on-chip is received. The packet-switched request is generated by source logic of the network-on-chip. Circuit-switched data associated with the packet switched request is also received. The circuit-switched data is stored by a storage element. The circuit-switched data is sent towards destination logic identified in the packet-switched request.
    Type: Grant
    Filed: December 17, 2014
    Date of Patent: June 5, 2018
    Assignee: Intel Corporation
    Inventors: Mark A. Anders, Himanshu Kaul, Gregory K. Chen
  • Patent number: 9979668
    Abstract: A first packet-switched reservation request is received. Data associated with the first packet-switched reservation request is communicated through a first circuit-switched channel according to a best effort communication scheme. A second packet-switched reservation request is received. Data associated with the second packet-switched reservation request is communicated through a second circuit-switched channel according to a guaranteed throughput communication scheme.
    Type: Grant
    Filed: December 22, 2014
    Date of Patent: May 22, 2018
    Assignee: Intel Corporation
    Inventors: Gregory K. Chen, Mark A. Anders, Himanshu Kaul, Ram K. Krishnamurthy, Aaron T. Stillmaker
  • Patent number: 9961019
    Abstract: A packet-switched reservation request to be associated with a first data stream is received. A communication mode is selected. The communication mode is to be either a circuit-switched mode or a packet-switched mode. At least a portion of the first data stream is communicated in accordance with the communication mode.
    Type: Grant
    Filed: December 22, 2014
    Date of Patent: May 1, 2018
    Assignee: Intel Corporation
    Inventors: Gregory K. Chen, Mark A. Anders, Himanshu Kaul, Ram K. Krishnamurthy, Yejoong Kim
  • Patent number: 9940236
    Abstract: A first pointer dereferencer receives a location of a portion of a first node of a data structure. The first node is to be stored in a first storage element. A first pointer is obtained from the first node of the data structure. A location of a portion of a second node of the data structure is determined based on the first pointer. The second node is to be stored in a second storage element. The location of the portion of the second node of the data structure is sent to a second pointer dereferencer that is to access the portion of the second node from the second storage element.
    Type: Grant
    Filed: December 17, 2014
    Date of Patent: April 10, 2018
    Assignee: Intel Corporation
    Inventors: Mark A. Anders, Himanshu Kaul, Gregory K. Chen
  • Patent number: 9923730
    Abstract: A multicast message that is to originate from a source is received. The multicast message comprises an identifier. A plurality of directions in which the multicast message is to fork at the router are stored. A plurality of messages from the directions in which the multicast message is to fork are received. The received messages are to comprise the identifier. The plurality of messages are aggregated into an aggregate message and sent towards the source.
    Type: Grant
    Filed: December 17, 2014
    Date of Patent: March 20, 2018
    Assignee: Intel Corporation
    Inventors: Gregory K. Chen, Mark A. Anders, Himanshu Kaul
  • Patent number: 9866476
    Abstract: A first packet and a first direction associated with the first packet are received. The first packet is forwarded to an output port of a plurality of output ports of the first router based on the first direction associated with the first packet. A second direction associated with the first packet is determined. The second direction is based at least on an address of the first packet. The first packet and the second direction are forwarded through the output port of the first router to a second router.
    Type: Grant
    Filed: December 17, 2014
    Date of Patent: January 9, 2018
    Assignee: Intel Corporation
    Inventors: Mark A. Anders, Gregory K. Chen, Himanshu Kaul
  • Patent number: 9843441
    Abstract: Embodiments of an invention for a compact, low power Advanced Encryption Standard circuit are disclosed. In one embodiment, an apparatus includes an encryption unit having a substitution box and an accumulator. The substitution box is to perform a substitution operation on one byte per clock cycle. The accumulator is to accumulate four bytes and perform a mix-column operation in four clock cycles. The encryption unit is implemented using optimum Galois Field polynomial arithmetic for minimum area.
    Type: Grant
    Filed: September 24, 2013
    Date of Patent: December 12, 2017
    Assignee: Intel Corporation
    Inventors: Sanu Mathew, Vikram Suresh, Sudhir Satpathy, Mark Anders, Himanshu Kaul, Ram Krishnamurthy
  • Patent number: 9787571
    Abstract: A router of a network-on-chip receives delay information associated with a plurality of links of the network-on-chip. The router determines at least one link of a data path based on the delay information.
    Type: Grant
    Filed: December 22, 2014
    Date of Patent: October 10, 2017
    Assignee: Intel Corporation
    Inventors: Vivek K. De, Ram K. Krishnamurthy, Gregory K. Chen, Mark A. Anders, Himanshu Kaul
  • Patent number: 9773336
    Abstract: Methods and systems for controlling the structure of animated documents are disclosed. In some embodiments, a method includes displaying, via a graphical user interface, a representation of a document, where the document includes a programmatic component configured to create an animation by manipulating a structure of the document, a static structure of the document corresponds to the structure of the document when the animation is not performed, and the animation, upon execution, is rendered starting from an original base state that at least partially defines the static structure. The method also includes, in response to receiving a selection corresponding to a state of the animation, designating the selected state as a new base state, wherein the new base state is different from the original base state. The method further includes altering the static structure of the document to correspond to the new base state.
    Type: Grant
    Filed: June 3, 2011
    Date of Patent: September 26, 2017
    Assignee: Adobe Systems Incorporated
    Inventors: Mark Anders, Joshua Hatwich, James W. Doubek, Joaquin Cruz Blas, Jr.
  • Patent number: 9699096
    Abstract: Disclosed herein is a router configured for priority-based routing. The router is configured to receive a plurality of packets, wherein each packet is assigned a priority value. The router includes an output circuit configured to select the packet with the highest priority value. The output circuit is configured to forward the priority value of the selected packet to a second router. The output circuit is configured to transfer the selected packet to the second router when the link between the first router and the second router is available.
    Type: Grant
    Filed: December 26, 2013
    Date of Patent: July 4, 2017
    Assignee: Intel Corporation
    Inventors: Sudhir Satpathy, Himanshu Kaul, Mark Anders, Sanu Mathew, Gregory Chen, Ram Krishnamurthy
  • Patent number: 9680765
    Abstract: An apparatus may comprise a plurality of ports and a plurality of channel reservation banks. A channel reservation bank is to be associated with a port of the plurality of ports. The channel reservation bank is to comprise a plurality of channel reservation slots. The port of the plurality of ports is to comprise a plurality of circuit-switched channels through the port. The configuration of each of the plurality of circuit-switched channels to be based on information stored in a channel reservation slot of the channel reservation bank to be associated with the port.
    Type: Grant
    Filed: December 17, 2014
    Date of Patent: June 13, 2017
    Assignee: Intel Corporation
    Inventors: Himanshu Kaul, Gregory K. Chen, Mark A. Anders
  • Patent number: 9680459
    Abstract: A signal comprising a first edge and a second edge is received. The first edge of the signal is synchronized with a first clock and the synchronized first edge of the signal is passed to an output. The synchronization results in a delay of the first edge of the signal. The second edge of the signal is passed to the output. The passed second edge of the signal has a delay that is less than the delay of the first edge of the signal by at least one clock cycle of the first clock.
    Type: Grant
    Filed: December 11, 2014
    Date of Patent: June 13, 2017
    Assignee: Intel Corporation
    Inventors: Gregory K. Chen, Mark A. Anders, Himanshu Kaul
  • Publication number: 20170150993
    Abstract: A device is configured to clear a bolus of food impacted within an esophagus, the device including a catheter tube having a hollow interior and a distal end configured to core the bolus of food and a proximal end configured to be coupled to a source of suction to clear the core.
    Type: Application
    Filed: November 21, 2016
    Publication date: June 1, 2017
    Inventors: Robert A. Ganz, Mark Anders Rydell
  • Publication number: 20170139948
    Abstract: Systems, apparatuses, and methods for k-nearest neighbor (KNN) searches are described. In particular, embodiments of a KNN accelerator and its uses are described. In some embodiments, the KNN accelerator includes a plurality of vector partial distance computation circuits each to calculate a partial sum, a minimum sort network to sort partial sums from the plurality of vector partial distance computation circuits to find k nearest neighbor matches and a global control circuit to control aspects of operations of the plurality of vector partial distance computation circuits.
    Type: Application
    Filed: November 18, 2015
    Publication date: May 18, 2017
    Inventors: Himanshu KAUL, Mark A. ANDERS, Sanu K. MATHEW
  • Patent number: 9652425
    Abstract: In an embodiment, a router includes multiple input ports and output ports, where the router is of a source-synchronous hybrid network on chip (NoC) to enable communication between routers of the NoC based on transitions in control flow signals communicated between the routers. Other embodiments are described and claimed.
    Type: Grant
    Filed: June 28, 2013
    Date of Patent: May 16, 2017
    Assignee: Intel Corporation
    Inventors: Gregory K. Chen, Mark A. Anders, Himanshu Kaul, Sudhir K. Satpathy, Ram K. Krishnamurthy