Abstract: Methods and apparatus provide for generating an image by way of acquiring information relating to at least one of a position and a rotation of a camera. The image is generated for display on a display unit. A rate at which the image is generated is at a first frequency, which is lower than a second frequency corresponding to a frame rate of the display unit.

Abstract: In one embodiment, an HSDPA co-processor for 3GPP Release 6 Category 8 (7.2 Mb/s) HSDPA that provides all chip-rate, symbol-rate, physical-channel, and transport-channel processing for HSDPA in 90 nm CMOS. The co-processor design is scalable to all HSDPA data rates up to 14 Mb/s. The coprocessor implements an Advanced Receiver based on an NLMS equalizer, supports RX diversity and TX diversity, and provides up to 6.4 dB better performance than a typical single-antenna rake receiver. Thus, 3GPP R6 HSDPA functionality can be added to a legacy R99 modem using an HSDPA co-processor consistent with embodiments of the present invention, at a reasonable incremental cost and power.

Abstract: In one embodiment, an OFDM transmitter generates sets of frequency-domain data symbols from a stream of digital data. For each set of frequency-domain data symbols generated, the transmitter generates a corresponding set of frequency-domain pilot symbols. Each corresponding set of data symbols and pilot symbols are then multiplexed onto a set of frequency tones, such that, at least one tone is occupied by both a data symbol and a pilot symbol. For each tone having both a pilot symbol and data symbol, the pilot symbol and data symbol are added together to form an overlaid data and pilot (ODP) tone. Each set of tones having at least one ODP tone is then transmitted to an inverse fast Fourier transform (IFFT) processor that transforms each set of tones into an ODP OFDM symbol. Each ODP OFDM symbol is then prepared for transmission using digital-to-analog conversion, cyclic prefix insertion, and RF modulation.

Abstract: A turbo decoder that calculates alpha, beta and gamma (branch metric) values does not normalize the branch metric but instead applies the normalization factor to the newly calculated extrinsic values before writing them to interleaving memory, resulting in use of less memory than in prior turbo decoders. A compensating factor is applied when the extrinsics are read from interleaving memory. The absence of normalization in the gamma calculation not only conserves memory but also enhances decoder sensitivity.

Abstract: Methods and apparatus are provided for block and rate independent decoding of LDPC codes. The disclosed LDPC decoders support multiple code block lengths and code rates, as well as a variable parity check matrix. The disclosed LDPC decoders decode LDPC codes that are based on a parity check matrix having a plurality of sub-matrices, wherein each row and column of the plurality of sub-matrices has a single entry. Each of the sub-matrices has at least one associated Phi-node, wherein each Phi-node comprises a memory device having a plurality of memory elements, wherein one or more of the memory elements may be selectively disabled. The Phi-nodes may be selectively disabled, for example, at run-time. The Phi-node optionally further comprises a multiplexer in order to provide a variable parity check matrix.

Abstract: An interleaver address generator is provided with pruning avoidance technology. It anticipates the points in time when incorrect addresses are computed by an IAG, and bypasses these events. It produces a stream of valid, contiguous addresses for all specified code block sizes. A single address computation engine firstly ‘trains’ itself about violating generated addresses (for a related block size) during the initial H1 half-iteration of decoder operation, and then produces a continuous, correct stream of addresses as required by the turbo decoder. Thus regions of pruned addresses are determined, and then training is performed only in these regions. Thus, computation and population of a pruned event table is determined in less than 1/10 the time required to do a conventional style full training. The resulting pruned event table is compressed down to 256 bits.

Abstract: A turbo decoder having two modes of operation decodes received information as per an N-state Radix-K trellis where N and K are integers equal to 1 or greater. The turbo decoder uses an in-line addressing technique that allows it to operate as a Serial Convolutional Code decoder in the first mode of operation and a Parallel Convolutional Code decoder in the second mode of operation. The decoder uses an in line addressing technique that allows it to use the same block of memory to store and retrieve states of the trellis as it processes received information. The turbo decoder can also operate as per an N-state Radix-K trellis where N is an integer equal to 2 or greater and K is an integer equal to 4 or greater.

Abstract: The invention provides apparatus (10) for separating dirt or dust from an airflow including a frustoconical cyclone (12) having a tangential air inlet (16) located at or adjacent the end of the cyclone having the larger diameter and a cone opening (18) located at the end of the cyclone having the smaller diameter. A collector (20) is arranged so as to surround the cone opening and has a base surface (24) facing towards the cone opening. According to the invention, at least a portion (24a) of the base surface is conical or frusto-conical in shape and a dust-retaining wall (30) is provided spaced from the center of the base surface.

Abstract: An apparatus (10) for separating dirt or dust from an airflow comprising a frustoconical cyclone (12) having a tangential air inlet (16) located at or adjacent the end of the cyclone (12) having the larger diameter and a cone opening (18) located at the end of the cyclone (12) having the smaller diameter is described. A collector (20) is arranged so as to surround the cone opening (18) and has a base surface (24) facing towards the cone opening (18). The distance between the cone opening (18) and the base surface (24) is between 4 and 6 mm or between 45 and 60 mm. The apparatus (10) is reduced in size without substantially affecting the separation efficiency.