Abstract: An in-circuit emulation debugger and method of operating an in-circuit emulation debugger to test a digital signal processor (DSP). In one embodiment, the in-circuit emulation debugger includes: (1) a device emulation unit, coupled to a collocated DSP core, for emulating circuitry that is to interact with the DSP core, (2) an external processor interface, coupled to the device emulation unit, that receives control signals from an external processor that cause the device emulation unit to provide a test environment for the DSP core and (3) a breakpoint detection circuit, associated with the device emulation unit, that responds to preprogrammed breakpoints based on occurrences of events both internal and external to the DSP core.

Abstract: A system and method are presented for an external host processor to distribute data to memory devices associated with multiple digital signal processors (DSPs) within an integrated circuit “system on a chip.” A host processor interface in the multi-processor integrated circuit responds to commands from the host processor and provides access to the memory devices. A control register in the interface is directly accessible by the host processor, and is used to generate various control signals in response to host processor commands. A data control register in the interface has a field of write enable bits that directly control write accessibility of the memory devices—if a designated write-enable bit within the data control register is set, the corresponding memory devices are write enabled. An extended address bit in the control register is used to select either instruction or data memory for write access.

Abstract: For use in a processor having an instruction cache, an instruction memory and an external synchronous memory, a memory management mechanism, a method of managing memory and a digital signal processor incorporating the mechanism or the method. In one embodiment, the mechanism includes an external memory request abort circuit coupled to the external synchronous memory and an instruction cache invalidator associated with the external memory request abort circuit. In this embodiment, the external memory request abort circuit aborts a request to load an instruction from the external synchronous memory before the information is loaded into the instruction cache. Additionally, the instruction cache invalidator invalidates the instruction cache when address spaces of the instruction memory and the external synchronous memory overlap and the processor switches between the instruction memory and the external synchronous memory.