Patents by Inventor Mark A. Brandyberry

Mark A. Brandyberry has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8843685
    Abstract: A presence detectable baffle for electrical components in a computing system, including: a passive chassis having a form factor is consistent with an electrical component of the computing system; and a presence detectable pin set connected to the passive chassis, the pin set consistent with the electrical component.
    Type: Grant
    Filed: September 6, 2011
    Date of Patent: September 23, 2014
    Assignee: International Business Machines Corporation
    Inventors: Mark A. Brandyberry, Todd W. Justus, Paul D. Kangas, Brent W. Yardley, Ivan R. Zapata
  • Patent number: 8812762
    Abstract: A presence detectable baffle for electrical components in a computing system, including: a passive chassis having a form factor is consistent with an electrical component of the computing system; and a presence detectable pin set connected to the passive chassis, the pin set consistent with the electrical component.
    Type: Grant
    Filed: June 27, 2012
    Date of Patent: August 19, 2014
    Assignee: International Business Machines Corporation
    Inventors: Mark A. Brandyberry, Todd W. Justus, Paul D. Kangas, Brent W. Yardley, Ivan R. Zapata
  • Patent number: 8521936
    Abstract: Administering computing system resources in a computing system, the computing system comprising at least one slot adapted to receive an electrical component having a set of pins, the slot configured to couple pins of the electrical component to the computing system, installed within the slot a presence detectable baffle, the presence detectable baffle comprising a passive chassis having a form factor consistent with the electrical component and a presence detectable pin set connected to the passive chassis, the pin set consistent with the electrical component, including: identifying, by a system manager, the presence detectable baffle; and managing, by the system manager, computing system operating attributes in dependence upon presence detectable baffle attributes.
    Type: Grant
    Filed: September 6, 2011
    Date of Patent: August 27, 2013
    Assignee: International Business Machines Corporation
    Inventors: Mark A. Brandyberry, Todd W. Justus, Paul D. Kangas, Brent W. Yardley, Ivan R. Zapata
  • Patent number: 8495269
    Abstract: Administering computing system resources in a computing system, the computing system comprising at least one slot adapted to receive an electrical component having a set of pins, the slot configured to couple pins of the electrical component to the computing system, installed within the slot a presence detectable baffle, the presence detectable baffle comprising a passive chassis having a form factor consistent with the electrical component and a presence detectable pin set connected to the passive chassis, the pin set consistent with the electrical component, including: identifying, by a system manager, the presence detectable baffle; and managing, by the system manager, computing system operating attributes in dependence upon presence detectable baffle attributes.
    Type: Grant
    Filed: June 21, 2012
    Date of Patent: July 23, 2013
    Assignee: International Business Machines Corporation
    Inventors: Mark A. Brandyberry, Todd W. Justus, Paul D. Kangas, Brent W. Yardley, Ivan R. Zapata
  • Publication number: 20130058031
    Abstract: A presence detectable baffle for electrical components in a computing system, including: a passive chassis having a form factor is consistent with an electrical component of the computing system; and a presence detectable pin set connected to the passive chassis, the pin set consistent with the electrical component.
    Type: Application
    Filed: September 6, 2011
    Publication date: March 7, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Mark A. Brandyberry, Todd W. Justus, Paul D. Kangas, Brent W. Yardley, Ivan R. Zapata
  • Publication number: 20130058037
    Abstract: A presence detectable baffle for electrical components in a computing system, including: a passive chassis having a form factor is consistent with an electrical component of the computing system; and a presence detectable pin set connected to the passive chassis, the pin set consistent with the electrical component.
    Type: Application
    Filed: June 27, 2012
    Publication date: March 7, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Mark A. Brandyberry, Todd W. Justus, Paul D. Kangas, Brent W. Yardley, Ivan R. Zapata
  • Publication number: 20130060984
    Abstract: Administering computing system resources in a computing system, the computing system comprising at least one slot adapted to receive an electrical component having a set of pins, the slot configured to couple pins of the electrical component to the computing system, installed within the slot a presence detectable baffle, the presence detectable baffle comprising a passive chassis having a form factor consistent with the electrical component and a presence detectable pin set connected to the passive chassis, the pin set consistent with the electrical component, including: identifying, by a system manager, the presence detectable baffle; and managing, by the system manager, computing system operating attributes in dependence upon presence detectable baffle attributes.
    Type: Application
    Filed: September 6, 2011
    Publication date: March 7, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Mark A. Brandyberry, Todd W. Justus, Paul D. Kangas, Brent W. Yardley, Ivan R. Zapata
  • Publication number: 20130060983
    Abstract: Administering computing system resources in a computing system, the computing system comprising at least one slot adapted to receive an electrical component having a set of pins, the slot configured to couple pins of the electrical component to the computing system, installed within the slot a presence detectable baffle, the presence detectable baffle comprising a passive chassis having a form factor consistent with the electrical component and a presence detectable pin set connected to the passive chassis, the pin set consistent with the electrical component, including: identifying, by a system manager, the presence detectable baffle; and managing, by the system manager, computing system operating attributes in dependence upon presence detectable baffle attributes.
    Type: Application
    Filed: June 21, 2012
    Publication date: March 7, 2013
    Applicant: International Business Machines Corporation
    Inventors: Mark A. Brandyberry, Todd W. Justus, Paul D. Kangas, Brent W. Yardley, Ivan R. Zapata
  • Patent number: 8041936
    Abstract: The last value of an element of a computing system is continually stored within a first register. The element is cleared during any restart or reset of the computing system. The last value is relevant to debugging of the computing system when the computing system fails to perform as expected and/or as desired. Upon receiving an instruction to reset the computing system via a first reset signal corresponding to pressing of a reset button or a second reset signal corresponding to a baseboard management controller issuing a reset command, the last value of the element as stored within the first register is copied to a second register. The computing system is then reset. The last value of the element as stored within the second register persists within the second register during this type of reset, but is cleared during any other reset or restart of the computing system.
    Type: Grant
    Filed: October 28, 2007
    Date of Patent: October 18, 2011
    Assignee: International Business Machines Corporation
    Inventors: Ryuji Orita, Mark A. Brandyberry, Mehul M. Shah, Sean P. Brogan
  • Patent number: 7594144
    Abstract: Methods and apparatus are disclosed for handling fatal computer hardware errors on a computer that include halting data processing operations of the computer upon occurrence of a fatal hardware error; signaling by a source chip of a chipset to the programmable logic device the occurrence of a fatal hardware error; signaling by the programmable logic device to an embedded system microcontroller the occurrence of a fatal hardware error; reading by the embedded system microcontroller through at least one sideband bus from registers in chips of the chipset information regarding the cause of the fatal hardware error; and storing by the embedded system microcontroller the information in non-volatile random access memory of the embedded system microcontroller.
    Type: Grant
    Filed: August 14, 2006
    Date of Patent: September 22, 2009
    Assignee: International Business Machines Corporation
    Inventors: Mark A. Brandyberry, Shiva R. Dasari, Daniel E. Hurlimann, Bruce J. Wilkie, Lee H. Wilson, Christopher L. Wood
  • Publication number: 20090113194
    Abstract: The last value of an element of a computing system is continually stored within a first register. The element is cleared during any restart or reset of the computing system. The last value is relevant to debugging of the computing system when the computing system fails to perform as expected and/or as desired. Upon receiving an instruction to reset the computing system via a first reset signal corresponding to pressing of a reset button or a second reset signal corresponding to a baseboard management controller issuing a reset command, the last value of the element as stored within the first register is copied to a second register. The computing system is then reset. The last value of the element as stored within the second register persists within the second register during this type of reset, but is cleared during any other reset or restart of the computing system.
    Type: Application
    Filed: October 28, 2007
    Publication date: April 30, 2009
    Inventors: Ryuji Orita, Mark A. Brandyberry, Mehul M. Shah, Sean P. Brogan
  • Patent number: 7478299
    Abstract: Methods, apparatus, and products for processor fault isolation are disclosed that include sending, by an embedded system microcontroller to a programmable logic device (‘PLD’) a selection signal identifying one processor for boundary scan operations; sending boundary scan input signals to be sent to the identified processor; multiplexing by the PLD the boundary scan input signals to the identified processor; and sending boundary scan output signals returned from the identified processor. Methods, apparatus, and products for processor fault isolation are also disclosed that include connecting two or more processors in a boundary scan test chain, the connecting carried out by a PLD of a computer, the PLD further connected to sense lines carrying presence signals indicating whether processors are present in the computer; and including in the chain all processors indicated present according to presence signals.
    Type: Grant
    Filed: August 14, 2006
    Date of Patent: January 13, 2009
    Assignee: International Business Machines Corporation
    Inventors: Mark A. Brandyberry, Lee H. Wilson
  • Publication number: 20080270827
    Abstract: Embodiments of the present invention address deficiencies of the art in respect to out-of-band management of system fault handling and provide a novel and non-obvious method, system and computer program product for recovering diagnostic data after out-of-band data capture failure. In an embodiment of the invention, a method for recovering diagnostic data after out-of-band data capture failure can include detecting an uncorrectable error in a coupled CPU. Thereafter, the coupled CPU can be placed in a quiesced state and the CPU can be warm reset. Error data can be retrieved from the CPU registers for the CPU and the CPU can be rebooted. Finally, the quiesced state of the CPU can be removed.
    Type: Application
    Filed: April 26, 2007
    Publication date: October 30, 2008
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Mark A. Brandyberry, Shiva R. Dasari, Jennifer L. Vargus
  • Publication number: 20080148003
    Abstract: Embodiments of the invention address deficiencies of the art in respect to parameter value configuration for signaling in a multi-drop net, and provide a novel and non-obvious method, system and apparatus for spatial based transceiver adjustment. In one embodiment of the invention, a spatial based dynamic transceiver configuration method can be provided for a multi-drop net. The method can include locating a position for a target receiver for signaling in the multi-drop net, selecting a static transceiver configuration corresponding to the position, and signaling the target receiver utilizing the selected static transceiver configuration. The locating, selecting and signaling can be repeated for different target receivers in different positions in the multi-drop net each repetition utilizing a different selected transceiver configuration.
    Type: Application
    Filed: December 19, 2006
    Publication date: June 19, 2008
    Inventors: Mark A. Brandyberry, Daniel N. de Araujo, Nickolaus J. Gruendler, Nam Huu Pham
  • Publication number: 20080126852
    Abstract: Methods and apparatus are disclosed for handling fatal computer hardware errors on a computer that include halting data processing operations of the computer upon occurrence of a fatal hardware error; signaling by a source chip of a chipset to the programmable logic device the occurrence of a fatal hardware error; signaling by the programmable logic device to an embedded system microcontroller the occurrence of a fatal hardware error; reading by the embedded system microcontroller through at least one sideband bus from registers in chips of the chipset information regarding the cause of the fatal hardware error; and storing by the embedded system microcontroller the information in non-volatile random access memory of the embedded system microcontroller.
    Type: Application
    Filed: August 14, 2006
    Publication date: May 29, 2008
    Inventors: Mark A. Brandyberry, Shiva R. Dasari, Daniel E. Hurlimann, Bruce J. Wilkie, Lee H. Wilson, Christopher L. Wood
  • Publication number: 20080052576
    Abstract: Methods, apparatus, and products for processor fault isolation are disclosed that include sending, by an embedded system microcontroller to a programmable logic device (‘PLD’) a selection signal identifying one processor for boundary scan operations; sending boundary scan input signals to be sent to the identified processor; multiplexing by the PLD the boundary scan input signals to the identified processor; and sending boundary scan output signals returned from the identified processor. Methods, apparatus, and products for processor fault isolation are also disclosed that include connecting two or more processors in a boundary scan test chain, the connecting carried out by a PLD of a computer, the PLD further connected to sense lines carrying presence signals indicating whether processors are present in the computer; and including in the chain all processors indicated present according to presence signals.
    Type: Application
    Filed: August 14, 2006
    Publication date: February 28, 2008
    Inventors: Mark A. Brandyberry, Lee H. Wilson