Abstract: A low resistance contact for p-type GaAs is provided by Pd/Zn/Pd/Au structure 1. The contact is suitable for device substrates having carrier concentrations in the range of about 10.sup.18 to about 10.sup.20 cm.sup.-3. The ohmic contact has a Pd layer of depth 3 nm to 15 nm, a Zn layer with a depth of between 5 nm and 40 nm, a second Pd layer with a depth greater than about 50 nm and an Au layer with a depth greater than about 300 nm. A preferred construction (1) is 5 nm/10 nm/100 nm/400 nm of Pd/Zn/Pd/Au. The ohmic contact deposition must be followed by annealing, with preferred annealing carried out at a temperature of about 200.degree. C. Annealing times are dependent upon annealing temperature, with a typical minimum annealing times of greater than 5 minutes at annealing temperatures of about 200.degree. C.

Abstract: A low resistance ohmic contact for n-type GaAs and GaAlAs is provided by Ni-Ge-Au structure (1). The contact is suitable for device substrates (2) which have carrier concentrations of between about 10.sup.17 cm.sup.-3 and about 10.sup.19 cm.sup.-3. The ohmic contact has a nickel layer of between 40 .ANG. and 200 .ANG. deposited on the substrate, followed by a Ge deposition (4) of between 150 .ANG. and 400 .ANG. and finally an Au deposition (5, 6) of greater than 4000 .ANG.. The Au layer is preferably deposited in two separate layers of between 500 .ANG. and 1000 .ANG., (5), and greater than 4000 .ANG., (6). A preferred construction (1) is 50 .ANG./200 .ANG./800 .ANG.+5000 .ANG. (Ni/Ge/Au+Au). The ohmic contact deposition must be followed by annealing, typically at temperatures between 300.degree. C. and 500.degree. C. for times of between 1 second and 200 seconds. The preferred annealing conditions are a temperature of 400.degree. C. maintained for 15 seconds.