Patents by Inventor Mark A. Eskew

Mark A. Eskew has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Non-volatile anti-fuse with consistent rupture
    Patent number: 9257440
    Abstract: In an embodiment of the invention, a non-volatile anti-fuse memory cell is disclosed. The memory cell consists of a programmable n-channel diode-connectable transistor. The poly-silicon gate of the transistor has two portions. One portion is doped more highly than a second portion. The transistor also has a source with two portions where one portion of the source is doped more highly than a second portion. The portion of the gate that is physically closer to the source is more lightly doped than the other portion of the poly-silicon gate. The portion of the source that is physically closer to the lightly doped portion of the poly-silicone gate is lightly doped with respect to the other portion of the source. When the transistor is programmed, a rupture in the insulator will most likely occur in the portion of the poly-silicone gate that is heavily doped.
    Type: Grant
    Filed: May 2, 2014
    Date of Patent: February 9, 2016
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Allan T. Mitchell, Mark A. Eskew, Keith Jarreau
  • NON-VOLATILE ANTI-FUSE WITH CONSISTENT RUPTURE
    Publication number: 20140239409
    Abstract: In an embodiment of the invention, a non-volatile anti-fuse memory cell is disclosed. The memory cell consists of a programmable n-channel diode-connectable transistor. The poly-silicon gate of the transistor has two portions. One portion is doped more highly than a second portion. The transistor also has a source with two portions where one portion of the source is doped more highly than a second portion. The portion of the gate that is physically closer to the source is more lightly doped than the other portion of the poly-silicon gate. The portion of the source that is physically closer to the lightly doped portion of the poly-silicone gate is lightly doped with respect to the other portion of the source. When the transistor is programmed, a rupture in the insulator will most likely occur in the portion of the poly-silicone gate that is heavily doped.
    Type: Application
    Filed: May 2, 2014
    Publication date: August 28, 2014
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Allan T. Mitchell, Mark A. Eskew, Keith Jarreau
  • Non-volatile anti-fuse with consistent rupture
    Patent number: 8748235
    Abstract: In an embodiment of the invention, a non-volatile anti-fuse memory cell is disclosed. The memory cell consists of a programmable n-channel diode-connectable transistor. The poly-silicon gate of the transistor has two portions. One portion is doped more highly than a second portion. The transistor also has a source with two portions where one portion of the source is doped more highly than a second portion. The portion of the gate that is physically closer to the source is more lightly doped than the other portion of the poly-silicon gate. The portion of the source that is physically closer to the lightly doped portion of the poly-silicone gate is lightly doped with respect to the other portion of the source. When the transistor is programmed, a rupture in the insulator will most likely occur in the portion of the poly-silicone gate that is heavily doped.
    Type: Grant
    Filed: August 8, 2012
    Date of Patent: June 10, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: Allan T. Mitchell, Mark A. Eskew, Keith Jarreau
  • NON-VOLATILE ANTI-FUSE WITH CONSISTENT RUPTURE
    Publication number: 20120313180
    Abstract: In an embodiment of the invention, a non-volatile anti-fuse memory cell is disclosed. The memory cell consists of a programmable n-channel diode-connectable transistor. The poly-silicon gate of the transistor has two portions. One portion is doped more highly than a second portion. The transistor also has a source with two portions where one portion of the source is doped more highly than a second portion. The portion of the gate that is physically closer to the source is more lightly doped than the other portion of the poly-silicon gate. The portion of the source that is physically closer to the lightly doped portion of the poly-silicone gate is lightly doped with respect to the other portion of the source. When the transistor is programmed, a rupture in the insulator will most likely occur in the portion of the poly-silicone gate that is heavily doped.
    Type: Application
    Filed: August 8, 2012
    Publication date: December 13, 2012
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Allan T. Mitchell, Mark A. Eskew, Keith Jarreau
  • Non-Volatile Anti-Fuse With Consistent Rupture
    Publication number: 20120228724
    Abstract: In an embodiment of the invention, a non-volatile anti-fuse memory cell is disclosed. The memory cell consists of a programmable n-channel diode-connectable transistor. The poly-silicon gate of the transistor has two portions. One portion is doped more highly than a second portion. The transistor also has a source with two portions where one portion of the source is doped more highly than a second portion. The portion of the gate that is physically closer to the source is more lightly doped than the other portion of the poly-silicon gate. The portion of the source that is physically closer to the lightly doped portion of the poly-silicone gate is lightly doped with respect to the other portion of the source. When the transistor is programmed, a rupture in the insulator will most likely occur in the portion of the poly-silicone gate that is heavily doped.
    Type: Application
    Filed: March 11, 2011
    Publication date: September 13, 2012
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Allan T. Mitchell, Mark A. Eskew, Keith Jarreau
  • Non-volatile anti-fuse with consistent rupture
    Patent number: 8258586
    Abstract: In an embodiment of the invention, a non-volatile anti-fuse memory cell is disclosed. The memory cell consists of a programmable n-channel diode-connectable transistor. The poly-silicon gate of the transistor has two portions. One portion is doped more highly than a second portion. The transistor also has a source with two portions where one portion of the source is doped more highly than a second portion. The portion of the gate that is physically closer to the source is more lightly doped than the other portion of the poly-silicon gate. The portion of the source that is physically closer to the lightly doped portion of the poly-silicone gate is lightly doped with respect to the other portion of the source. When the transistor is programmed, a rupture in the insulator will most likely occur in the portion of the poly-silicone gate that is heavily doped.
    Type: Grant
    Filed: March 11, 2011
    Date of Patent: September 4, 2012
    Assignee: Texas Instruments Incorporated
    Inventors: Allan T. Mitchell, Mark A. Eskew, Keith Jarreau