Patents by Inventor Mark A. Finn
Mark A. Finn has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230193441Abstract: A system for heat-treating a coil of metal can include a furnace, an unwinding system, and a quenching system. The furnace may receive the coil of metal and elevate a temperature of the metal to be within a pre-heated temperature range, such as a homogenizing temperature range or an annealing temperature range. The unwinding system may unwind at least a portion of the coil in a heated state in which the metal is within the pre-heated temperature range or before the metal has cooled past a threshold amount below the pre-heated temperature range. The quenching system may receive the unwound portion of the coil from the unwinding device and reduce a temperature of the unwound portion to a within a quenched temperature range within a predetermined amount of time.Type: ApplicationFiled: October 13, 2020Publication date: June 22, 2023Applicant: Novelis Inc.Inventors: Timothy Francis Stanistreet, Mark Finn, Renato Rufino Xavier, Frank Su, Louis Mitchell Nazro, Tudor Piroteala, Samuel Robert Wagstaff, Barbara Lucille Hyde, David Anthony Gaensbauer, Sazol Kumar Das
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Patent number: 11499213Abstract: Systems and methods of threading a metal substrate on a rolling mill include receiving a coil of the metal substrate. The method also includes uncoiling the metal substrate from the coil while the coil and guiding the metal substrate to a work stand of the rolling mill with a threading system.Type: GrantFiled: June 21, 2019Date of Patent: November 15, 2022Assignee: Novelis Inc.Inventors: Andrew James Hobbis, Antoine Jean Willy Pralong, Stephen Lee Mick, Rodger Brown, Mark Finn, Peter Knelsen, Terry Lee, Hansjuerg Alder, William Beck, Roberto Quintal, Natasha Iyer, Jeffrey Edward Geho
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Patent number: 11377721Abstract: Systems and methods of threading a metal substrate on a rolling mill include receiving a coil of the metal substrate. The method also includes uncoiling the metal substrate from the coil while the coil and guiding the metal substrate to a work stand of the rolling mill with a threading system.Type: GrantFiled: June 21, 2019Date of Patent: July 5, 2022Assignee: Novelis Inc.Inventors: Andrew James Hobbis, Antoine Jean Willy Pralong, Stephen Lee Mick, Rodger Brown, Mark Finn, Peter Knelsen, Terry Lee, Hansjuerg Alder, William Beck, Roberto Quintal, Natasha Iyer, Jeffrey Edward Geho
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Patent number: 11242586Abstract: Systems and methods of threading a metal substrate on a rolling mill include receiving a coil of the metal substrate. The method also includes uncoiling the metal substrate from the coil while the coil and guiding the metal substrate to a work stand of the rolling mill with a threading system.Type: GrantFiled: June 21, 2019Date of Patent: February 8, 2022Assignee: Novelis Inc.Inventors: Andrew James Hobbis, Antoine Jean Willy Pralong, Stephen Lee Mick, Rodger Brown, Mark Finn, Peter Knelsen, Terry Lee, Hansjuerg Alder, William Beck, Roberto Quintal, Natasha Iyer, Jeffrey Edward Geho
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Publication number: 20190330725Abstract: Systems and methods of threading a metal substrate on a rolling mill include receiving a coil of the metal substrate. The method also includes uncoiling the metal substrate from the coil while the coil and guiding the metal substrate to a work stand of the rolling mill with a threading system.Type: ApplicationFiled: June 21, 2019Publication date: October 31, 2019Applicant: NOVELIS INC.Inventors: ANDREW JAMES HOBBIS, ANTOINE JEAN WILLY PRALONG, STEPHEN LEE MICK, RODGER BROWN, MARK FINN, PETER KNELSEN, TERRY LEE, HANSJUERG ALDER, WILLIAM BECK, ROBERTO QUINTAL, NATASHA IYER, JEFFREY EDWARD GEHO
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Publication number: 20190309404Abstract: Systems and methods of threading a metal substrate on a rolling mill include receiving a coil of the metal substrate. The method also includes uncoiling the metal substrate from the coil while the coil and guiding the metal substrate to a work stand of the rolling mill with a threading system.Type: ApplicationFiled: June 21, 2019Publication date: October 10, 2019Applicant: NOVELIS INC.Inventors: ANDREW JAMES HOBBIS, ANTOINE JEAN WILLY PRALONG, STEPHEN LEE MICK, RODGER BROWN, MARK FINN, PETER KNELSEN, TERRY LEE, HANSJUERG ALDER, WILLIAM BECK, ROBERTO QUINTAL, NATASHA IYER, JEFFREY EDWARD GEHO
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Publication number: 20190309403Abstract: Systems and methods of threading a metal substrate on a rolling mill include receiving a coil of the metal substrate. The method also includes uncoiling the metal substrate from the coil while the coil and guiding the metal substrate to a work stand of the rolling mill with a threading system.Type: ApplicationFiled: June 21, 2019Publication date: October 10, 2019Applicant: NOVELIS INC.Inventors: ANDREW JAMES HOBBIS, ANTOINE JEAN WILLY PRALONG, STEPHEN LEE MICK, RODGER BROWN, MARK FINN, PETER KNELSEN, TERRY LEE, HANSJUERG ALDER, WILLIAM BECK, ROBERTO QUINTAL, NATASHA IYER, JEFFREY EDWARD GEHO
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Patent number: 10370749Abstract: Systems and methods of threading a metal substrate on a rolling mill include receiving a coil of the metal substrate. The method also includes uncoiling the metal substrate from the coil while the coil and guiding the metal substrate to a work stand of the rolling mill with a threading system.Type: GrantFiled: September 27, 2017Date of Patent: August 6, 2019Assignee: Novelis Inc.Inventors: Andrew James Hobbis, Antoine Jean Willy Pralong, Stephen Lee Mick, Rodger Brown, Mark Finn, Peter Knelsen, Terry Lee, Hansjuerg Alder, William Beck, Roberto Quintal, Natasha Iyer, Jeffrey Edward Geho
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Publication number: 20180085803Abstract: Systems and methods of threading a metal substrate on a rolling mill include receiving a coil of the metal substrate. The method also includes uncoiling the metal substrate from the coil while the coil and guiding the metal substrate to a work stand of the rolling mill with a threading system.Type: ApplicationFiled: September 27, 2017Publication date: March 29, 2018Applicant: Novelis Inc.Inventors: Andrew James Hobbis, Antoine Jean Willy Pralong, Stephen Lee Mick, Rodger Brown, Mark Finn, Peter Knelsen, Terry Lee, Hansjuerg Alder, William Beck, Roberto Quintal, Natasha Iyer, Jeffrey Edward Geho
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Patent number: 6910164Abstract: A method for testing a semiconductor memory device includes forcing the device into a logic state configuration that does not occur during normal operation of the device. The method may also include holding the logic state configuration for a user-variable length of time. In an embodiment, the device testing method includes flowing a direct current through a first input node of a bi-stable latch. This node may be electrically arranged between a node coupled to a voltage source and a node coupled to a circuit ground potential. An embodiment of a memory device may include testmode circuitry adapted to maintain a pair of bitlines at logic states that are not maintained during ordinary operation of the device. A system for testing a semiconductor memory device may include testmode circuitry adapted to force a pair of bitlines to the same logic state for a user-determined length of time.Type: GrantFiled: August 9, 2001Date of Patent: June 21, 2005Assignee: Cypress Semiconductor Corp.Inventor: Mark Finn
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Patent number: 6286118Abstract: A circuit for delaying a signal. The circuit includes a scan register, a logic circuit, and a programmable delay circuit. The scan register stores scan data and the logic circuit selectively decodes the scan data. The programmable delay circuit is coupled to the logic circuit and delays a signal a programmable amount of time in response to the decoded scan data.Type: GrantFiled: July 21, 1998Date of Patent: September 4, 2001Assignee: Cypress Semiconductor CorporationInventors: Jonathan F. Churchill, Neil P. Raftery, Colin J. Hendry, Jeyakumar Shanmugam, Mark A. Finn, Thomas M. Surrette, Cathal G. Phelan, Ashish Pancholy
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Patent number: 6115836Abstract: A circuit for generating a pulse including a scan register having a first scan bit; first logic device receiving a first signal and generating a second signal; and a programmable delay circuit coupled to the scan register and the first logic device. The programmable delay circuit receives the second signal and generates a delayed second signal after a programmable period of time. The programmable period of time is determined by the first scan bit. The circuit also includes a logic circuit that recevies the second signal and the delayed second signal. The logic circuiit outputs the pulse having a pulse width proportional to the programmable period of time.Type: GrantFiled: September 17, 1997Date of Patent: September 5, 2000Assignee: Cypress Semiconductor CorporationInventors: Jonathan F. Churchill, Neil P. Raftery, Colin J. Hendry, Jeyakumar Shanmugam, Mark A. Finn, Thomas M. Surrette, Cathal G. Phelan, Ashish Pancholy
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Patent number: 6006347Abstract: An integrated circuit including a first input for receiving a scan enable control signal and a second input for receiving a test mode control signal. The integrated circuit also includes a programmable scan circuit coupled to the first input and the second input. The programmable scan circuit configures the integrated device to operate in a default mode, a scan mode, or a test mode in response to the scan enable and test mode control signals.Type: GrantFiled: September 17, 1997Date of Patent: December 21, 1999Assignee: Cypress Semiconductor CorporationInventors: Jonathan F. Churchill, Neil P. Raftery, Colin J. Hendry, Jeyakumar Shanmugam, Mark A. Finn, Thomas M. Surrette, Cathal G. Phelan, Ashish Pancholy
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Patent number: 5953285Abstract: A circuit including a register coupled to a control circuit. The register has a synchronous mode of operation and an asynchronous mode of operation. The a control circuit controls whether the register operates in the synchronous mode or the asynchronous mode. The circuit may further include a scan register having scan data. The control circuit may cause the register to operate in the synchronous or asynchronous mode in response to the scan data.Type: GrantFiled: September 17, 1997Date of Patent: September 14, 1999Assignee: Cypress Semiconductor Corp.Inventors: Jonathan F. Churchill, Neil P. Raftery, Jeyakumar Shanmugam, Mark A. Finn, Thomas M. Surrette, Cathal G. Phelan, Ashish Pancholy
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Patent number: 5936977Abstract: A circuit for delaying a signal. The circuit includes a scan register, a logic circuit, and a programmable delay circuit. The scan register stores scan data and the logic circuit selectively decodes the scan data. The programmable delay circuit is coupled to the logic circuit and delays a signal a programmable amount of time in response to the decoded scan data.Type: GrantFiled: September 17, 1997Date of Patent: August 10, 1999Assignee: Cypress Semiconductor Corp.Inventors: Jonathan F. Churchill, Neil P. Raftery, Colin J. Hendry, Jeyakumar Shanmugam, Mark A. Finn, Thomas M. Surrette, Cathal G. Phelan, Ashish Pancholy