Patents by Inventor Mark A. Gaertner
Mark A. Gaertner has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20190103146Abstract: In accordance with one implementation, a method for reducing cache service time includes determining an access time parameter associated with movement of a read/write head to an access location for each of a plurality of contiguous cache storage segments and dynamically selecting one of the plurality of contiguous cache storage segments to store data based on the determined access time parameter.Type: ApplicationFiled: September 29, 2017Publication date: April 4, 2019Inventors: Andrew Michael Kowles, Mark Gaertner, Xiong Liu, WenXiang Xie, Kai Yang, Jiangnan Lin
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Publication number: 20190026134Abstract: An application programming interface (API) that enables installation of an application as one or more key-value objects on a data storage drive such as a hard disk drive, a solid state drive or a hybrid drive. The API also enables execution of the application within a controlled environment of the data storage drive.Type: ApplicationFiled: September 12, 2018Publication date: January 24, 2019Inventors: Jon D. Trantham, Timothy T. Walker, Mark A. Gaertner, Christopher A. Markey, Chiaming Yang, Bryan D. Wyatt
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Patent number: 10180792Abstract: Data storage devices may store selected data received from a data source to a buffer memory. The selected data may be copied from the buffer to a non-volatile memory configured for sequential storage. The selected data may then be copied from the buffer to a solid state memory, such as dynamic random access memory. The selected data may be copied from the solid state memory to a main store, such as a magnetic disc memory. If the selected data cannot be found in the solid state memory, the selected data in the non-volatile memory can be copied to the main store.Type: GrantFiled: April 30, 2015Date of Patent: January 15, 2019Assignee: Seagate Technology LLCInventors: Mark Gaertner, James D Sawin
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Publication number: 20190013086Abstract: A data storage system can consist of a number of data storage devices each having a non-volatile memory, a memory buffer, and an error detection module. The memory buffer may store a first data block comprising a front-end first-level error detection code assigned by the error detection module. The non-volatile memory can consist of a second data block having a back-end first-level error detection code and a second-level error detection code each assigned by the error detection module.Type: ApplicationFiled: July 7, 2017Publication date: January 10, 2019Inventors: Thomas V. Spencer, Ryan James Goss, Mark A. Gaertner
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Patent number: 10176886Abstract: A data storage system can consist of a number of data storage devices each having a non-volatile memory, a memory buffer, and an error detection module. The memory buffer may store a first data block comprising a front-end first-level error detection code assigned by the error detection module. The non-volatile memory can consist of a second data block having a back-end first-level error detection code and a second-level error detection code each assigned by the error detection module.Type: GrantFiled: July 7, 2017Date of Patent: January 8, 2019Assignee: Seagate Technology LLCInventors: Thomas V. Spencer, Ryan James Goss, Mark A. Gaertner
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Publication number: 20180359227Abstract: A method includes adding a key version tag to an encryption key store that stores encryption keys. The key version tag is inserted into a data stream. The data stream including the key version tag is written to media. The data in the data stream is erased by scrambling the encryption keys and incrementing the key version tag in the encryption store by a digit. The data stream is replaced with a replacement data pattern when the key version tag stored in the encryption store and the key version tag located in the data stream mismatch.Type: ApplicationFiled: June 12, 2017Publication date: December 13, 2018Inventors: Jon D. Trantham, Mark A. Gaertner, Monty Aaron Forehand, Paul Michael Wiggins
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Publication number: 20180335976Abstract: Embodiments described herein are operable in a computing system. The computing system receives first and second commands (e.g., I/O commands). The computing system determines that the first command has a higher priority than the second I/O command, and queues the second command for servicing at a later time. The computing system services the first command, and services the second command after a timeout period based on performance degradation limit that decreases command processing performance of the computing system, overrides the timeout period, and increases a probability of executing the second command.Type: ApplicationFiled: May 19, 2017Publication date: November 22, 2018Inventors: Jeffrey V. DeRosa, Ling Zhi Yang, Kenneth L. Barham, Mark A. Gaertner
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Patent number: 10108481Abstract: Systems and methods are disclosed to perform early termination error recovery at a data storage device. A data storage device may be configured to perform error recovery operations in response to encountering an error while executing a host command, and terminate the error recovery operations prior to completion based on an error recovery time limit. Based on early termination of the error recovery operations, the storage device can add a storage location corresponding to the error to a scan list of storage locations on which to perform additional error recovery operations. In some embodiments, the host may set the error recovery time limit.Type: GrantFiled: February 18, 2016Date of Patent: October 23, 2018Assignee: Seagate Technology LLCInventors: Abhay T Kataria, Mark A Gaertner
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Patent number: 10102145Abstract: Systems and methods are disclosed to perform out of order LBA processing at a data storage device. A data storage device may be configured to receive a read command including a sequential LBA range, read data for the LBA range in non-sequential order and store the data to a buffer, and return the data to the host in sequential LBA order. The storage device may begin a read operation at a sector in the middle of the LBA range, and read the beginning of the LBA range on a next rotation of the media. The storage device may note the location of read errors without interrupting a read operation. Successfully read data may be buffered, while rereads and error recovery may be performed only on LBAs at which errors were encountered. Once the data from the LBA range has been acquired, the data may be organized into sequential order.Type: GrantFiled: December 7, 2015Date of Patent: October 16, 2018Assignee: Seagate Technology LLCInventors: Richard P Michel, Mark A Gaertner, Kevin Nghia Dao
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Publication number: 20180121364Abstract: A data storage device includes a storage tier and a storage controller operably coupled to the storage tier and configured to be communicatively coupled to a host device. The storage controller includes a first memory operably coupled to the storage controller and configured to store a superseding data structure. The storage controller further includes a second memory operably coupled to the storage controller and configured to store a forward map configured to map a plurality of logical block addresses to physical locations on the storage tier. The storage controller further includes a sifting module configured to sift the forward map based on data contained in the superseding data structure. The storage controller further includes a compression module configured to compress the forward map to generate a compressed forward map.Type: ApplicationFiled: October 27, 2016Publication date: May 3, 2018Inventors: Brian T. Edgar, Mark A. Gaertner, John Livdahl
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Patent number: 9921774Abstract: The disclosure is related to systems and methods of managing data storage in a memory device. In a particular embodiment, a method is disclosed that includes receiving, in a data storage device, at least one data packet that has a size that is different from an allocated storage capacity of at least one physical destination location on a data storage medium in the data storage device for the at least one data packet. The method also includes storing the at least one received data packet in a non-volatile cache memory prior to transferring the at least one received data packet to the at least one physical destination location.Type: GrantFiled: February 2, 2016Date of Patent: March 20, 2018Assignee: Seagate Technology LLCInventors: Luke W. Friendshuh, Brian T. Edgar, Mark A. Gaertner
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Publication number: 20180018269Abstract: A hybrid data storage device disclosed herein includes a main data store, one or more data storage caches, and a data storage cache management sub-system. The hybrid data storage device is configured to limit write operations on the one or more data storage caches to less than an endurance value for the data storage cache. In one implementation, the data storage cache management sub-system limits or denies requests for promotion of data from the main data store to the one or more data storage caches. In another implementation, the data storage cache management sub-system limits garbage collection operations on the data storage cache.Type: ApplicationFiled: July 13, 2016Publication date: January 18, 2018Inventors: Sumanth Jannyavula Venkata, Mark A. Gaertner, Jonathan G. Backman
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Patent number: 9842060Abstract: A hybrid data storage device disclosed herein includes a main data store, one or more data storage caches, and a data storage cache management sub-system. The data storage cache may be divided into an over-provisioned portion and an advertised space portion. Clusters of data on the data storage cache corresponding to the over-provisioned portion are marked as pending eviction rather than actually evicted when the data storage cache management sub-system receives a write request, thereby increasing the effective capacity and reducing write amplification of the data storage cache.Type: GrantFiled: July 13, 2016Date of Patent: December 12, 2017Assignee: SEAGATE TECHNOLOGY LLCInventors: Sumanth Jannyavula Venkata, Mark A. Gaertner, Jonathan G. Backman
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Patent number: 9740406Abstract: A data storage system includes data storage and random access memory. A sorting module is communicatively coupled to the random access memory and sorts data blocks of write data received in the random access memory of the data storage. A storage controller is communicatively coupled to the random access memory and the data storage and being configured to write the sorted data blocks into one or more individually-sorted granules in a granule storage area of the data storage, wherein each granule is dynamically constrained to a subset of logical block addresses. A method and processor-implemented process provide for sorting data blocks of write data received in random access memory of data storage. The method and processor-implemented process write the sorted data blocks into one or more individually-sorted granules in a granule storage area of the data storage, wherein each granule is dynamically constrained to a subset of logical block addresses.Type: GrantFiled: June 8, 2016Date of Patent: August 22, 2017Assignee: SEAGATE TECHNOLOGY LLCInventors: Mark A. Gaertner, Brian Thomas Edgar
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Patent number: 9741436Abstract: In general, this disclosure is directed to techniques for adjusting the timing of operations for a storage device. According to one aspect of the disclosure, a method includes receiving, with at least one device, a workload indicator. The method further includes adjusting, with the at least one device, an operation execution time for the storage device responsive to at least the workload indicator. In some examples, the workload indicator may include a host demand indicator. In additional examples, the workload indicator may include a resource utilization indicator. In further examples, the operation execution time may be one of a write operation execution time or a read operation execution time.Type: GrantFiled: July 9, 2010Date of Patent: August 22, 2017Assignee: SEAGATE TECHNOLOGY LLCInventors: Ryan J. Goss, Kevin A. Gomez, Mark A. Gaertner
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Patent number: 9588887Abstract: A data storage system includes data storage and random access memory. A sorting module is communicatively coupled to the random access memory and is configured to sort data blocks of incoming write data received in the random access memory. A storage controller is communicatively coupled to the random access memory and the data storage and is configured to write the sorted data blocks as individually-sorted data block sets to a staging area of the data storage. A method and processor-implemented process provide for sorting data blocks of incoming write data received in a random access memory of data storage and writing the sorted data blocks as individually-sorted data block sets to a staging area of the data storage.Type: GrantFiled: August 22, 2013Date of Patent: March 7, 2017Assignee: SEAGATE TECHNOLOGY LLCInventors: Brian Thomas Edgar, Mark A. Gaertner
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Patent number: 9588886Abstract: A data storage system includes data storage and random access memory. A sorting module is communicatively coupled to the random access memory and is configured to sort data blocks of incoming write data received in the random access memory. A storage controller is communicatively coupled to the random access memory and the data storage and is configured to write the sorted data blocks as individually-sorted data block sets to a staging area of the data storage. A method and processor-implemented process provide for sorting data blocks of incoming write data received in a random access memory of data storage and writing the sorted data blocks as individually-sorted data block sets to a staging area of the data storage.Type: GrantFiled: March 15, 2013Date of Patent: March 7, 2017Assignee: SEAGATE TECHNOLOGY LLCInventors: Brian Thomas Edgar, Mark A. Gaertner
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Patent number: 9552252Abstract: Certain exemplary aspects of the present disclosure are directed towards methods and apparatuses in which logic circuitry generates an error detection code based on user data received from a host, and further generates a first set of check bits, to be written to the non-volatile memory circuit in conjunction with the user data, by combining the error detection code with a hashed data address of the user data. In some embodiments, the check bits associated with the user data providing verification that the user data was written in the appropriate physical block address of the non-volatile memory circuit.Type: GrantFiled: August 25, 2014Date of Patent: January 24, 2017Assignee: Seagate Technology LLCInventors: Jon D. Trantham, Brian T. Edgar, Mark Gaertner, Bruce Buch
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Publication number: 20160283115Abstract: A data storage system includes data storage and random access memory. A sorting module is communicatively coupled to the random access memory and sorts data blocks of write data received in the random access memory of the data storage. A storage controller is communicatively coupled to the random access memory and the data storage and being configured to write the sorted data blocks into one or more individually-sorted granules in a granule storage area of the data storage, wherein each granule is dynamically constrained to a subset of logical block addresses. A method and processor-implemented process provide for sorting data blocks of write data received in random access memory of data storage. The method and processor-implemented process write the sorted data blocks into one or more individually-sorted granules in a granule storage area of the data storage, wherein each granule is dynamically constrained to a subset of logical block addresses.Type: ApplicationFiled: June 8, 2016Publication date: September 29, 2016Inventors: Mark A. Gaertner, Brian Thomas Edgar
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Patent number: 9396062Abstract: A multi-dimensional recording (MDR) system may include a group based coding circuit (GBCC) which can implement error correcting codes via outer codes. The GBCC can implement outer codes, including interleaving outer codes, in MDR systems where inner codewords include multiple memory groupings. The multiple memory groupings may be across different structural divisions within a data storage medium; or could be across multiple different data storage mediums.Type: GrantFiled: April 4, 2014Date of Patent: July 19, 2016Assignee: SEAGATE TECHNOLOGY LLCInventors: Deepak Sridhara, William Radich, Ara Patapoutian, Timothy R Feldman, Mark Gaertner