Abstract: A multi-finger high-electron mobility transistor and a method of manufacturing such a transistor, and an electronic device including such a transistor is provided. According to an aspect of the present disclosure, an etching step for reducing donor layer thickness and/or performing an ion implantation is used for locally reducing the 2DEG concentration.

Abstract: The present disclosure relates to a semiconductor device, and associated method of manufacture. The semiconductor device includes, MOSFET integrated with a p-n junction, the p-n junction arranged as a clamping diode across a source contact and a drain contact of the MOSFET. The MOSFET defines a first breakdown voltage and the clamping diode defines a second breakdown voltage, with the first breakdown voltage being greater than the second breakdown voltage so that the clamp diode is configured and arranged to receive a low avalanche current and the MOSFET is configured and arranged to receive a high avalanche current.

Abstract: The present disclosure relates to a semiconductor device, and associated method of manufacture. The semiconductor device includes, MOSFET integrated with a p-n junction, the p-n junction arranged as a clamping diode across a source contact and a drain contact of the MOSFET. The MOSFET defines a first breakdown voltage and the clamping diode defines a second breakdown voltage, with the first breakdown voltage being greater than the second breakdown voltage so that the clamp diode is configured and arranged to receive a low avalanche current and the MOSFET is configured and arranged to receive a high avalanche current.

Abstract: Various aspects of the disclosure are directed to circuitry coupled for controlling current flow, such as in a cascode arrangement. As may be consistent with one or more embodiments, an apparatus includes a first transistor having a gate, source, channel and drain, and a second transistor having a gate, and having a stacked source, channel and drain. A conductive clip plate electrically connects the drain of the second transistor to the source of the first transistor, and another conductor electrically connects the source of the second transistor to the gate of the first transistor. The second transistor operates with the connecting structure to provide power by controlling the first transistor in an off-state and in an on-state.

Abstract: Various aspects of the disclosure are directed to circuitry coupled for controlling current flow, such as in a cascode arrangement. As may be consistent with one or more embodiments, an apparatus includes a first transistor having a gate, source, channel and drain, and a second transistor having a gate, and having a stacked source, channel and drain. A conductive clip plate electrically connects the drain of the second transistor to the source of the first transistor, and another conductor electrically connects the source of the second transistor to the gate of the first transistor. The second transistor operates with the connecting structure to provide power by controlling the first transistor in an off-state and in an on-state.

Abstract: A semiconductor device has a first region (10) and a second region (20), gate trenches (50) being formed in paid first and second regions including insulated gates to control conduction between source regions (42) and a common drain region (40) through a body region separated into first (34) and second (36) body regions. Isolation between the first and second regions is provided in a simple way by providing a gap between the first and second body regions (34,36) formed by eg. at least one trench (52) or a part of the drain region.

Abstract: The trench-gate (11) of, for example, a cellular power MOSFET comprises doped poly-Si or other semiconductor material (11a) adjacent to the gate dielectric layer (17) adjacent to the channel-accommodating region (15) of the device. The gate (11) also comprises a sizeable silicide part (11b) that reduces gate resistance. This silicide part (11b) protrudes upwardly from the trench (20) over a distance (z) typically larger than the width (w) of the trench (20), so forming an upstanding part (11b) of a metal silicide material between its top and sidewalls above the level of the body surface (10a). The gate dielectric layer (17) at least adjacent to the channel-accommodating region (15) is protected from the metal silicide by at least the semiconductor part (11a) of the gate and by the protrusion (z) of the silicide part (11b) upwardly above the level of the body surface (10a).

Abstract: In a cellular power MOSFET or other semiconductor device, a wide connection across the perimeter of an active device area (120) is replaced with a plurality of narrower conducting fingers (111). The fingers (11) are used as follows in providing a doped edge region (15a) that is required below the connection (110). Dopant (150,151) is implanted at spaces (112) between and beside the fingers (111) and is diffused to form a single continuous region (15a) extending beneath the fingers (111) and at the spaces (112) therebetween. This doped edge region (15a) may be, for example, a deep guard ring in an edge termination of a power MOSFET, or an extension of its channel-accommodating region (15). A trench-gate network (11) of the MOSFET can be connected by the conducting fingers to a gate bond pad and/or field plate (114).

Abstract: The trench-gate (11) of, for example, a cellular power MOSFET comprises doped poly-Si or other semiconductor material (11a) adjacent to the gate dielectric layer (17) adjacent to the channel-accommodating region (15) of the device. The gate (11) also comprises a sizeable silicide part (11b) that reduces gate resistance. This silicide part (11b) protrudes upwardly from the trench (20) over a distance (z) typically larger than the width (w) of the trench (20), so forming an upstanding part (11b) of a metal silicide material between its top and sidewalls above the level of the body surface (10a). The gate dielectric layer (17) at least adjacent to the channel-accommodating region (15) is protected from the metal silicide by at least the semiconductor part (11a) of the gate and by the protrusion (z) of the silicide part (11b) upwardly above the level of the body surface (10a).

Abstract: The trench-gate (11) of, for example, a cellular power MOSFET comprises doped poly-Si or other semiconductor material (11a) adjacent to the gate dielectric layer (17) adjacent to the channel-accommodating region (15) of the device. The gate (11) also comprises a sizeable silicide part (11b) that reduces gate resistance. This silicide part (11b) protrudes upwardly from the trench (20) over a distance (z) typically larger than the width (w) of the trench (20), so forming an upstanding part (11b) of a metal silicide material between its top and sidewalls above the level of the body surface (10a). The gate dielectric layer (17) at least adjacent to the channel-accommodating region (15) is protected from the metal silicide by at least the semiconductor part (11a) of the gate and by the protrusion (z) of the silicide part (11b) upwardly above the level of the body surface (10a).

Abstract: In a cellular power MOSFET or other semiconductor device, a wide connection across the perimeter of an active device area (120) is replaced with a plurality of narrower conducting fingers (111). The fingers (11) are used as follows in providing a doped edge region (15a) that is required below the connection (110). Dopant (150,151) is implanted at spaces (112) between and beside the fingers (111) and is diffused to form a single continuous region (15a) extending beneath the fingers (111) and at the spaces (112) therebetween. This doped edge region (15a) may be, for example, a deep guard ring in an edge termination of a power MOSFET, or an extension of its channel-accommodating region (15). A trench-gate network (11) of the MOSFET can be connected by the conducting fingers to a gate bond pad and/or field plate (114).

Abstract: The trench-gate (11) of, for example, a cellular power MOSFET comprises doped poly-Si or other semiconductor material (11a) adjacent to the gate dielectric layer (17) adjacent to the channel-accommodating region (15) of the device. The gate (11) also comprises a sizeable silicide part (11b) that reduces gate resistance. This silicide part (11b) protrudes upwardly from the trench (20) over a distance (z) typically larger than the width (w) of the trench (20), so forming an upstanding part (11b) of a metal silicide material between its top and sidewalls above the level of the body surface (10a). The gate dielectric layer (17) at least adjacent to the channel-accommodating region (15) is protected from the metal silicide by at least the semiconductor part (11a) of the gate and by the protrusion (z) of the silicide part (11b) upwardly above the level of the body surface (10a).

Abstract: A trench gate field effect device has a semiconductor body (2) with a trench (3) extending into a first major surface (2a) so as to define a regular array of polygonal source cells (4). Each source cell contains a source region (5a,5b) and a body region (6a,6b) with the body regions separating the source regions from a common further region (20). A gate (G) extends within and along said trench (3) for controlling a conduction channel through each of the body regions. Each source cell (4) has a central semiconductor region (60) which is more highly doped than said body regions, is of opposite conductivity type to the further region and forms a diode with the further region. Each source cell (4) has an inner trench boundary (3a) and an outer polygonal trench boundary (3b) with the inner trench boundary bounding a central subsidiary cell (10a) containing the central semiconductor region (60).