Abstract: A system includes a focal plane array (FPA), support structure, optical assembly, flexing structure, and drive actuator. The FPA includes multiple pixels. The FPA captures an image as image data during an integration time interval. The optical assembly is fixed to the support structure and forms an image of a scene at the FPA. The flexing structure is mechanically coupled to both the support structure and the FPA, and allows the FPA to move relative to the support structure. The actuator is mechanically coupled to the FPA, and drives the FPA to move relative to the support structure. Some FPA have all readout elements arranged in a first regular grid with constant spacing, while some detector elements are on that grid and other detector elements are on a different grid offset by less than the constant spacing to provide sub-pixel resolution.

Abstract: An imaging solution that uses a small, adaptable, real-time, scalable, image-processing (SMARTS IP) chip configured to function like any one of a wide range of specialized FPA imaging devices, and a method for configuring and implementing same is provided. Configuration for a wide range of applications and implementations, including ones with or without IDCA assemblies or other types of dewar/cooler structures, is disclosed. A wide range of output data formats, including all SDI-compatible image data formats, may be accomplished. Frame stacking and variable effective resolution and charge well depth levels may be accomplished in output image data based on on-chip image processing techniques. On-chip image processing algorithms may include XR™, DRC, NUC, and other similar or related techniques. Image data output compression through on-chip processing is also disclosed.

Abstract: An imaging solution that uses a small, adaptable, real-time, scalable, image-processing (SMARTS IP) chip configured to function like any one of a wide range of specialized FPA imaging devices, and a method for configuring and implementing same is provided. Configuration for a wide range of applications and implementations, including ones with or without IDCA assemblies or other types of dewar/cooler structures, is disclosed. A wide range of output data formats, including all SDI-compatible image data formats, may be accomplished. Frame stacking and variable effective resolution and charge well depth levels may be accomplished in output image data based on on-chip image processing techniques. On-chip image processing algorithms may include XR™, DRC, NUC, and other similar or related techniques. Image data output compression through on-chip processing is also disclosed.

Abstract: An apparatus and method for acquiring image data from a scanned, multi-bank time-delay and integrate (TDI) focal plane array (FPA) detector. Specifically a method and apparatus for warping and combining sequentially-acquired image data of a scene portion from multiple TDI detector banks into a single image having improved image quality, thereby providing improved FPA sensitivity. Also, a method and apparatus for enabling sensitivity and areal rate trade-offs in a multi-bank, scanning TDI FPA based on the number of TDI banks being used for sequential imaging of the same scene portion.

Abstract: An imaging solution that uses a small, adaptable, real-time, scalable, image-processing (SMARTS IP) chip configured to function like any one of a wide range of specialized FPA imaging devices, and a method for configuring and implementing same is provided. Configuration for a wide range of applications and implementations, including ones with or without IDCA assemblies or other types of dewar/cooler structures, is disclosed. A wide range of output data formats, including all SDI-compatible image data formats, may be accomplished. Frame stacking and variable effective resolution and charge well depth levels may be accomplished in output image data based on on-chip image processing techniques. On-chip image processing algorithms may include XR™, DRC, NUC, and other similar or related techniques. Image data output compression through on-chip processing is also disclosed.

Abstract: An imaging circuit comprises an image detector, accumulator coupled to the image detector, a focus/defocus mechanism focusing and defocusing an optical image onto the image detector; and a controller operatively connected to the focus/defocus mechanism, wherein the controller controls the focus/defocus mechanism to focus and defocus the optical image onto the image detector to provide focused and defocused images; where the controller controls the focus/defocus mechanism to focus the optical image onto the image detector to provide charge carriers of the focused image onto the accumulator, where the accumulator accumulates the charge carriers of the focused image, the controller controls the focus/defocus mechanism to defocus the optical image onto the image detector to provide charge carriers of the defocused image onto the accumulator, where the accumulator subtracts the charge carriers of the defocused image, and the imaging circuit reads out the charge carriers from the accumulator representative of a low

Abstract: An apparatus and method for acquiring image data from a scanned, multi-bank time-delay and integrate (TDI) focal plane array (FPA) detector. Specifically a method and apparatus for warping and combining sequentially-acquired image data of a scene portion from multiple TDI detector banks into a single image having improved image quality, thereby providing improved FPA sensitivity. Also, a method and apparatus for enabling sensitivity and areal rate trade-offs in a multi-bank, scanning TDI FPA based on the number of TDI banks being used for sequential imaging of the same scene portion.

Abstract: A current mirror circuit 10 is coupled to a first and a second photodetector 18 and 20 and differentially couples together the two photodetectors to an amplifier 12 such that a resulting differential output current is independent of the intrinsic responsivity difference between the two photodetectors. The circuit includes a first transistor 14 having an input terminal coupled to an output terminal of the first photodetector and a second transistor 16 having an input terminal coupled to an output terminal of the second photodetector. A capacitance 22 is coupled between a control terminal of the first transistor and a control terminal of the second transistor, the control terminal of the first transistor further being coupled to the input terminal of the first transistor. A first switch 24 is coupled between the control terminal of the second transistor and the input terminal of the second transistor.

Abstract: A transresistance amplifier particularly adapted for use in a radiation detection system. The amplifier includes a feedback gain stage with a switched capacitor load. The amplifier is arranged to provide an average detector voltage approximating zero thus substantially reducing detector noise and also providing a low equivalent input impedance for increasing injection efficiency. A switched capacitor output load is also provided which allows the total transresistance to be determined by simply selecting an appropriate capacitance value.

Abstract: A transresistance amplifier particularly adapted for use in a radiation detection system. The amplifier includes a feedback gain stage with a switched capacitor load. The amplifier is arranged to provide an average detector voltage approximating zero thus substantially reducing detector noise and also providing a low equivalent input impedance for increasing injection efficiency. A switched capacitor output load is also provided which allows the total transresistance to be determined by simply selecting an appropriate capacitance value.