Abstract: A circuit, apparatus and method obtains system margin at the receive circuit using phase shifted data sampling clocks while allowing the CDR to remain synchronized with the incoming data stream in embodiments. In an embodiment, a circuit includes first and second samplers to sample a data signal and output data and edge information in response to a data clock signal and an edge clock signal. A phase detector generates phase information in response to the data information and the edge information. A clock phase adjustment circuit generates the data clock signal and the edge clock signal in response to the data information during a synchronization mode. The clock phase adjustment circuit increments a phase of the data clock signal during a waveform capture mode.

Abstract: Method and apparatus for allowing a person with disabilities to learn to pedal a conventional bicycle which device also converts a conventional bicycle into an in-place exercise bike. In the bike trainer embodiment, the device allows the training wheels which are attached to the rear wheel of a bicycle to be elevated by being placed in a right and left trough of the base of the device so that the rear wheel of the bicycle is elevated off the ground and spins freely in a space between the right and left troughs. In the exercise bicycle embodiment, an adjustable rear roller assembly can be attached to the base of the device so that the rear wheel of the bicycle rests on a pair of rollers so as to allow the rear wheel of the bicycle to contact and roll on a front and rear roller so as to increase pedaling resistance while the front wheel of the bicycle is stabilized by a stand having a pair of adjustable upright members and a pair of laterally extending members for maintaining the bicycle in a stable position.

Abstract: A signaling system is described. The signaling system comprises a transmit device, a receive device including a partial response receive circuit, and a signaling path coupling the transmit device and the receive device. The receive device observes an equalized signal from the signaling path, and includes circuitry to use feedback from the most recent previously resolved symbol to sample a currently incoming symbol. The transmit device equalizes transmit data to transmit the equalized signal, by applying weighting based on one or more data values not associated with the most recent previously resolved symbol value.

Abstract: A multiphase receiver to compensate for intersymbol interference in the sampling of an input signal includes a first integrating receiver to integrate and sample data of the input signal on a first phase of a clock and a second integrating receiver to integrate and sample data of the input signal on a second phase of the clock. The multiphase receiver also includes an equalization circuit to adjust integration by the first integrating receiver dependent on a result of integration of data previously received by an integrating receiver distinct from the first integrating receiver, and to adjust integration by the second integrating receiver dependent on a result of integration of data previously received by an integrating receiver distinct from the second integrating receiver.

Abstract: Light-field microscopy is facilitated using an approach to image computation. In connection with an example embodiment, a subject (e.g., 105) is imaged by passing light from the subject through a microlens array (e.g., 120) to a photosensor array (e.g., 130) to simultaneously detect light from the subject that is passed through different directions to different locations. In certain embodiments, information from the detected light is used to compute refocused images, perspective images and/or volumetric datasets, from a single-shot photograph.

Abstract: A high-speed signaling system with adaptive transmit pre-emphasis. A transmit circuit has a plurality of output drivers to output a first signal onto a signal path. A receive circuit is coupled to receive the first signal via the signal path and configured to generate an indication of whether the first signal exceeds a threshold level. A first threshold control circuit is coupled to receive the indication from the receive circuit and configured to adjust the threshold level according to whether the first signal exceeds the threshold level. A drive strength control circuit is coupled to receive the indication from the receive circuit and configured to adjust a drive strength of at least one output driver of the plurality of output drivers according to whether the first signal exceeds the threshold level.

Abstract: A receive circuit for receiving a signal transmitted via an electric signal conductor. A first sampling circuit generates a first sample value that indicates whether the signal exceeds a first threshold level, and a second sampling circuit generates a second sample value that indicates whether the signal exceeds a second threshold level. A first select circuit receives the first and second sample values from the first and second sampling circuits and selects, according to a previously generated sample value, either the first sample value or the second sample value to be output as a selected sample value.

Abstract: A receive circuit for receiving a signal transmitted via an electric signal conductor. A first sampling circuit generates a first sample value that indicates whether the signal exceeds a first threshold level, and a second sampling circuit generates a second sample value that indicates whether the signal exceeds a second threshold level. A first select circuit receives the first and second sample values from the first and second sampling circuits and selects, according to a previously generated sample value, either the first sample value or the second sample value to be output as a selected sample value.

Abstract: A memory system is disclosed comprising a memory controller and a first set of volatile memory devices defining a first memory hierarchy. The first set of volatile memory devices are disposed on at least one first memory module, which is coupled to the memory controller in a daisy-chained configuration. A first integrated circuit buffer device is included on the module. The system has a second set of nonvolatile memory devices defining a second memory hierarchy. The second set of nonvolatile memory devices are disposed on at least one second memory module, which is coupled to the at least one first memory module in a daisy-chained configuration. The second module includes a second integrated circuit buffer device. The system is configured such that signals transmitted between the memory controller and the second memory hierarchy pass through the first memory hierarchy.

Abstract: An integrated circuit device having a receive circuit is disclosed. The receive circuit generates first and second sets of samples of incoming symbols during first and second time intervals, respectively. A select circuit selects, based at least in part on the first set of samples, at least one sample from the second set to be output as a received data value. The integrated circuit device further includes a transmit circuit to generate an output symbol during a third time interval. The output symbol has an amplitude based, at least in part, on a transmit data value for which an output symbol was generated during a time interval prior to the third time interval.

Abstract: A system and method for performing clock data recovery. The system sets the phase of a recovered clock signal 30 according to at least three estimates of the rate of change of an offset between the frequency of the data transmitter clock and the frequency of a receiver clock 15.

Abstract: A first integrated circuit is coupled to a first connector. A second connector is coupled to the first connector through multiple conductors, in which alternating pairs of conductors are reversed. A second integrated circuit is coupled to the second connector through a second group of conductors. The first integrated circuit includes multiple differential drivers and the second integrated circuit includes multiple differential receivers. The inductive coupling coefficient of the first device is modified to be substantially the same as the inductive coupling coefficient of the second device.

Abstract: Described are communication systems that convey differential and common-mode signals over the same differential channel. Noise-tolerant communication schemes use low-amplitude common-mode signals that are easily rejected by differential receivers, thus allowing for very high differential data rates. Some embodiments employ the common-mode signals to transmit backchannel signals for adjusting the characteristics of the differential transmitter. Backchannel control signals are effectively conveyed even if the forward channel transmitter is so maladjusted that the received differential data is unrecognizable. Systems in accordance with the above-described embodiments obtain these advantages without additional pins or communications channels, and are compatible with both AC-coupled and DC-coupled communications channels. Data coding schemes and corresponding data recovery circuits eliminate the need for complex, high-speed CDR circuits.

Abstract: An integrated circuit device (100) includes structures (104) that exhibit performance degradation as a function of use (e.g., accumulated defects within the tunneling oxide of a Flash memory cell, or trapped charge within a charge storage layer) and heating circuitry (101) disposed in proximity to the structures to heat the structures to a temperature that reverses the degradation. The word lines or the bit lines of the memory device are used as heating elements (107).

Abstract: Various approaches to imaging involve selecting directional and spatial resolution. According to an example embodiment, images are computed using an imaging arrangement to facilitate selective directional and spatial aspects of the detection and processing of light data. Light passed through a main lens is directed to photosensors via a plurality of microlenses. The separation between the microlenses and photosensors is set to facilitate directional and/or spatial resolution in recorded light data, and facilitating refocusing power and/or image resolution in images computed from the recorded light data. In one implementation, the separation is varied between zero and one focal length of the microlenses to respectively facilitate spatial and directional resolution (with increasing directional resolution, hence refocusing power, as the separation approaches one focal length).

Abstract: A high-speed signaling system with adaptive transmit pre-emphasis. A transmit circuit has a plurality of output drivers to output a first signal onto a signal path. A receive circuit is coupled to receive the first signal via the signal path and configured to generate an indication of whether the first signal exceeds a threshold level. A first threshold control circuit is coupled to receive the indication from the receive circuit and configured to adjust the threshold level according to whether the first signal exceeds the threshold level. A drive strength control circuit is coupled to receive the indication from the receive circuit and configured to adjust a drive strength of at least one output driver of the plurality of output drivers according to whether the first signal exceeds the threshold level.

Abstract: A method of simulating device mismatch effects on transient circuit behaviors utilizes a circuit model corresponding to an electronic circuit. The circuit model includes a plurality of circuit elements and one or more noise sources. The noise sources have noise characteristics that correspond to device mismatch effects associated with the circuit elements. A noise analysis is performed on the circuit model to generate a noisy steady-state waveform of a selected output of the electronic circuit. Then, the noisy steady-state waveform is translated into a prediction of the variation of a respective circuit parameter associated with the electronic circuit.

Abstract: A system includes a first integrated circuit device and a second integrated circuit device. The first device transmits a data sequence to the second integrated circuit device, and the second device samples the data sequence to produce receiver data. The second device then transmits the receiver data back to the first device. Within the first integrated circuit device, a comparison between the data sequence and the receiver data is performed, and based on the comparison, the first device generates information representative of a calibrated timing offset. The first device uses the information representative of the calibrated timing offset to adjust timing associated with transferring write data from the first integrated circuit to the second integrated circuit.

Abstract: A memory system uses multiple pulse amplitude modulation (multi-PAM) output drivers and receivers to send and receive multi-PAM signals. A multi-PAM signal has more than two voltage levels, with each data interval now transmitting a “symbol” at one of the valid voltage levels. In one embodiment, a symbol represents two or more bits. The multi-PAM output driver drives an output symbol onto a signal line. The output symbol represents at least two bits that include a most significant bit (MSB) and a least significant bit (LSB). The multi-PAM receiver receives the output symbol from the signal line and determines the MSB and the LSB.

Abstract: A first integrated circuit is coupled to a first connector. A second connector is coupled to the first connector through multiple conductors, in which alternating pairs of conductors are reversed. A second integrated circuit is coupled to the second connector through a second group of conductors. The first integrated circuit includes multiple differential drivers and the second integrated circuit includes multiple differential receivers. The inductive coupling coefficient of the first device is modified to be substantially the same as the inductive coupling coefficient of the second device.