Abstract: A microprocessor is provided which detects dependencies among instructions. The microprocessor assigns each instruction to a processing element or elements which perform the operation specified by the instruction. Additionally, the microprocessor is configured to dynamically alter the interconnect between the processing elements such that dependent operations receive operands from the operations upon which they depend. In particular, an instruction which computes a result upon which another instruction depends is connected to provide the result to that instruction. Routing of data between processing elements is determined prior to the execution of the instructions. Using the dynamic reconfiguration of interconnections, the microprocessor executes instruction sequences more efficiently than a DSP which is optimized for another instruction sequence.

Abstract: A CPU or microprocessor which includes a general purpose CPU, such as an X86 core, and a DSP. The CPU also includes an intelligent DSP function decoder or preprocessor which examines X8 opcode sequences and determines if a DSP function is being executed. The function preprocessor includes a look-up table which stores instruction sequences which implement DSP functions. Each pattern in the look-up table is compared with an instruction sequence to determine if one of the patterns substantially matches the instruction sequence. If the DSP function preprocessor determines that a DSP function is being executed, the DSP function preprocessor converts the opcodes to a DSP macro instruction that is provided to the DSP. The DSP executes one or more DSP instructions to implement the desired DSP function in response to the macro instruction. If the X86 opcodes in the instruction cache or instruction memory do not indicate or are not intended to perform a DSP-type function, the opcodes are provided to the X86 core.

Abstract: A CPU or microprocessor which includes a general purpose CPU component, such as an X86 core, and also includes a DSP core. The CPU also includes an intelligent DSP function decoder or preprocessor which examines X86 opcode sequences and determines if a DSP function is being executed. If the DSP function decoder determines that a DSP function is being executed, the DSP function decoder converts or maps the opcodes to a DSP macro instruction that is provided to the DSP core. The DSP core executes one or more DSP instructions to implement the desired DSP function in response to the macro instruction. The DSP core implements or performs the DSP function using a lesser number of instructions and also in reduced number of clock cycles, thus increasing system performance. If the X86 opcodes in the instruction cache or instruction memory do not indicate or are not intended to perform a DSP-type function, the opcodes are provided to the X86 core as which occurs in current prior art computer systems.

Abstract: A vocoder for generating speech from a plurality of stored speech parameters which computes the excitation signals in the speech production model. The present invention generates a periodic excitation signal with flat frequency response and linear group delay. The present invention uses properties of the phase delay sequence being generated to calculate each of the parameters of the excitation signal in an efficient and optimized manner. Generation of the excitation signal requires computation of the expression: ##EQU1## The above expression uses the equation: ##EQU2## This equation defines the phase relationship between the signals using a linear group delay where .phi.'.sub.I (x)* is the absolute phase offset from the first phase harmonic, I is an index for the harmonic, x is time, P is the pitch period, and k" is a constant. The present invention performs the following iterations to compute the above sequence:1) .phi.'.sub.I (x)*=.phi.'.sub.I- (x)*+A.sub.I-1 (x)2) A.sub.I (x)=A.sub.I-1 (x)-Bwhere A.sub.

Abstract: An improved vocoder system and method for estimating pitch in a speech waveform which more accurately disregards false pitch estimates resulting from secondary excitations. The vocoder system first performs a correlation calculation on a speech frame and generates an estimated pitch value. The present invention then compares the estimated or determined pitch with a threshold value to determine if the determined or estimated pitch has a suspiciously low pitch value. If so, the present invention performs error checking to disregard pitch estimates that are the result of the First Formant frequency's contribution to the pitch estimation process. The error checking involves examining the higher multiples of the determined pitch value to ascertain whether the determined pitch value might be incorrect. The present invention determines whether one or more higher multiples are missing, whether the higher multiples are related by a common factor, and whether adjacent multiples have missing peaks.

Abstract: A CPU or microprocessor which includes a general purpose CPU, such as an X86 core, and a DSP. The CPU also includes an intelligent DSP function decoder or preprocessor which examines X86 opcode sequences and determines if a DSP function is being executed. The function preprocessor includes a pattern recognition detector which stores instruction sequences which implement DSP functions. The pattern recognition detector compares each pattern with an instruction sequence and determines if one of the patterns substantially matches the instruction sequence. If the DSP function preprocessor determines that a DSP function is being executed, the preprocessor converts or maps the opcodes to a DSP macro instruction that is provided to the DSP. The DSP executes one or more DSP instructions to implement the desired DSP function in response to the macro instruction.

Abstract: An apparatus and method for locating a plurality of roots of a line spectrum pair expression on a unit circle.

Abstract: A microprocessor including an instruction decode unit configured to detect a DSP call instruction is provided. The DSP call instruction is indicative of a call to a subroutine which performs a DSP function. Detected DSP call instructions are routed to a DSP which executes a routine performing the corresponding function. Subsequent to the DSP completing execution of the routine, the microprocessor continues execution at the instruction subsequent to the DSP call instruction. If a DSP is not included in the computer system, the DSP call instruction is executed in a manner similar to a subroutine call instruction. The microprocessor subsequently executes a corresponding routine which performs the DSP function.

Abstract: A system and method for calculating linear predictive coding (lpc) coefficients in response to a received speech signal waveform. The system of the present invention uses a method referred to as the FLAT method for computing the lpc coefficients. The FLAT method involves computing 10 lpc filter coefficients and proceeds in a succession of iterations, wherein the 10 filter coefficients are derived in part from 10 reflection coefficients. According to the present invention, the method determines or predicts a scaling factor and, during each iteration, applies the scaling factor to the matrix terms prior to storage of the data while the full precision value is still available internally. Thus the present invention maintains full precision for the speech data during the computation. The scale factor prediction method of the present invention is most effective for high power voiced speech where the greatest loss of precision occurs using prior art post-storage scaling techniques.

Abstract: A superscalar microprocessor is provided that includes a plurality of execution units each configured to execute the same subset of instructions. The subset of instructions may include arithmetic instructions and instructions optimized for performing DSP functionality. Instructions are routed to each of the execution units from an instruction decode unit. Each execution unit includes a plurality reservation stations for storing the instructions awaiting execution. The superscalar microprocessor advantageously includes an instruction reroute unit configured to determine whether a pending instruction within a reservation station of a particular execution unit must wait for more than a predetermined number of clock cycles before the execution unit can begin its execution.

Abstract: An apparatus and method for synthesizing a sinusoidal signal generated from a plurality of sample values taken at sample times in succeeding sample intervals. The signal is defined by a parameter which varies by a step value during predetermined sample intervals when the parameter changes from a first value to a second value. The apparatus includes a first logic unit for iteratively treating an initial step value to generate succeeding samples of the step value and a next step value. The next step value is the step value in a next-succeeding sample interval. A second logic unit is included for iteratively generating a next parameter value which is the parameter value during the next-succeeding sample interval. The second logic unit receives succeeding samples of the step value and iteratively generates succeeding samples of an interim parameter value and succeeding samples of a derivative interim parameter value.

Abstract: An apparatus and method for discriminating and suppressing noise within an incoming signal including a first signal processor to generate a first signal representing the incoming signal; a second signal processor to generate a second signal representing the first signal; a prediction device which generates a prediction for the second signal; a logic device which determines the difference between the second signal and the prediction and generates a logic output having a first value when the difference exceeds a threshold and a second value when the difference does not exceed the threshold; and a muting device to mute the incoming signal when the logic output has one value and not mute the incoming signal when the logic output has the other value.

Abstract: A method is described for encoding a first image to produce a second, lower resolution image. For each superpixel group in the first image, a prediction class is formed, based on the values of the pixels in two adjacent superpixels. This prediction class is used to access a table, to obtain a prediction for the corresponding pixel in the second image. If the prediction matches the actual pixel pattern of the superpixel, the corresponding pixel in the second image is set to the predicted colour. If the prediction does not match, then the corresponding pixel in the second image is set to the inverse of the predicted colour, and the actual pixel pattern is stored in a supplementary file. If no prediction is provided, the actual pixel pattern is stored, and the pixel in the second image is set to the colour of the majority of the pixels in the superpixel.