Abstract: Apparatus and methods for measuring characteristics of a metallic target as well as other interior surfaces of a sputtering chamber. The apparatus includes a sensor configured to emit an energy beam toward a surface of interest and to detect an energy beam therefrom, the detected energy beam being indicative of parameters of a characteristic of interest of the surface of interest. Quantitative and qualitative characteristics of interest may be determined. A sputtering system including the apparatus and operable according to the methods of the invention is also disclosed.

Abstract: An apparatus and method for measuring the erosion profile of a metallic target in a sputtering device are provided by inserting a thin sensor into a gap between the target and a substrate pedestal. The sensor is configured to emit an energy beam toward the surface of the target and detect a reflection of the energy beam. The sensor may comprise a source element configured to emit a collimated light beam and a plurality of detectors arranged in a linear array. The sensor may also comprise optical fibers configured to reduce the size of the sensor. The detectors are positioned relative to the source element so that one of the detectors in the array will be illuminated by a reflection of the collimated light beam. The distance from the sensor to the target may be derived from the position of the detector illuminated by the reflected beam.

Abstract: An apparatus and method for measuring the erosion profile of a metallic target in a sputtering device is provided by inserting a thin sensor into a gap between the target and a substrate pedestal. The sensor is configured to emit an energy beam toward the surface of the target and to detect a reflection of the energy beam. The sensor may comprise a source element configured to emit a collimated light beam and a plurality of detectors arranged in a linear array. The sensor may also comprise optical fibers configured to reduce the size of the sensor. The detectors are positioned relative to the source element so that one of the detectors in the array will be illuminated by a reflection of the collimated light beam. The distance from the sensor to the target may be derived from the position of the detector illuminated by the reflected beam.

Abstract: A method and apparatus is provided for planarizing damascene metallic circuit patterns of a plurality of discrete integrated circuit chips on a metal coated silicon wafer wherein the circuitry on the chips on the wafer are either designed to be within a defined high metal density circuit range and low density metal circuit range and/or to provide dummy circuitry in the damascene process to provide a substantially uniform circuit density over the chip and the wafer surface. It is preferred that each chip on the surface of the wafer be divided into a plurality of regions and that each region be provided with dummy metallization, if necessary, to provide a relatively uniform circuit density in that region and consequently on the wafer surface. The invention also contemplates adding dummy circuitry to the periphery of the wafer in areas which are not formed into chips (chip fragments). The invention also provides semiconductor wafers made using the method and/or apparatus of the invention.

Abstract: In a chemical-mechanical polishing (CMP) process, semiconductor substrates are rotated against a polishing pad in order to planarize substrate layers. The condition of the polishing pad directly affects the polishing rate of material removal and uniformity of removal from the semiconductor wafer. Conditioning of the polishing pad surface with an abrasive improves polishing uniformity and rates, however, it has the detrimental affect of removing a quantity of pad material. A method and apparatus for monitoring polishing pad wear during processing is developed to extend the pad's useful life, and maintain pad uniformity. This is accomplished in the present invention by measuring and monitoring the diminished pad thickness using a non-intrusive measurement system, and creating a closed-loop system for adjusting the chemical-mechanical polishing tool process parameters.

Abstract: A method for depositing materials on a surface, having the following steps: a) obtaining a surface having at least feature thereon, the surface and the feature having a layer of first material deposited thereon, the first material not filling substantially all of the feature; b) depositing a layer of a second material on the first material, wherein the melting point of the second material is less than that of the first material, and wherein the first material is soluble in the second material at a temperature less than the melting point of the first material; and c) heating the surface to a first temperature of at least equal to the melting point of the second material and at most equal to the melting point of the first material, wherein substantially all of the via is filled with the first material.

Abstract: An integrated circuit including a capacitor and a method of manufacturing the capacitor simultaneously while forming a dual damascene via. A first interconnect layer is formed upon a first interlevel dielectric. Openings corresponding to vias and capacitors extend through a second interlevel dielectric to the first interconnect layer. A conductor is deposited in the via openings. An insulator is deposited in the openings and on the conductor in the via openings. A trench is then etched into the upper portion of the via openings while simultaneously removing the insulator from the conductor in the via openings. A conductor is then deposited in the openings and in the trenches and chemical-mechanical polishing (CMP) is used to pattern the conductor. A third interlevel dielectric is then deposited, openings are formed extending to the conductors, and third interconnect layer conductors are deposited and patterned.

Abstract: A process for reducing polish stop erosion includes using a slurry of particles and an alkaline solution. The slurry for reducing polish stop erosion has a reduced solids content, finer particle size, and an increased chemical component. The pH of the slurry is between about 9.5 and 10.5.

Abstract: A semiconductor device having areas that are semiconductor on insulator ("SOI") and areas that are bulk, single crystalline semiconductive areas is provided in which conductive spacers may be formed to electrically connect the SOI areas to ground in order to overcome floating body effects that can occur with SOI. Additionally, insulative spacers may be formed on the surface of the conductive spacers to electrically isolate the SOI regions from the bulk regions. A novel method for making both of these products is provided in which the epitaxially grown, single crystalline bulk regions need not be selectively grown, because a sacrificial polishing layer is deposited, is also provided.

Abstract: A method and apparatus is provided for planarizing damascene metallic circuit patterns of a plurality of discrete integrated circuit chips on a metal coated silicon wafer wherein the circuitry on the chips on the wafer are either designed to be within a defined high metal density circuit range and low density metal circuit range and/or to provide dummy circuitry in the damascene process to provide a substantially uniform circuit density over the chip and the wafer surface. It is preferred that each chip on the surface of the wafer be divided into a plurality of regions and that each region be provided with dummy metallization, if necessary, to provide a relatively uniform circuit density in that region and consequently on the wafer surface. The invention also contemplates adding dummy circuitry to the periphery of the wafer in areas which are not formed into chips (chip fragments). The invention also provides semiconductor wafers made using the method and/or apparatus of the invention.

Abstract: A method and apparatus for monitoring polishing pad wear during processing is developed to extend the pad's useful life, and maintain pad uniformity. This is accomplished in the present invention by measuring and monitoring the diminished pad thickness using a non-intrusive measurement system, and creating a closed-loop system for adjusting the chemical-mechanical polishing tool process parameters. The non-intrusive measurement system consists of an interferometer measurement technique utilizing ultrasound or electromagnetic radiation transmitters and receivers aligned to cover any portion of the radial length of a polishing pad surface. The measurement system is sensitive to relative changes in pad thickness for uniformity, and to abrupt changes such as detecting wafer detachment from the CMP wafer carrier.

Abstract: An integrated circuit including a capacitor and a method of manufacturing the capacitor simultaneously while forming a dual damascene via. A first interconnect layer is formed upon a first interlevel dielectric. Openings corresponding to vias and capacitors extend through a second interlevel dielectric to the first interconnect layer. A conductor is deposited in the via openings. An insulator is deposited in the openings and on the conductor in the via openings. A trench is then etched into the upper portion of the via openings while simultaneously removing the insulator from the conductor in the via openings. A conductor is then deposited in the openings and in the trenches and chemical-mechanical polishing (CMP) is used to pattern the conductor. A third interlevel dielectric is then deposited, openings are formed extending to the conductors, and third interconnect layer conductors are deposited and patterned.

Abstract: A semiconductor device having areas that are semiconductor on insulator ("SOI") and areas that are bulk, single crystalline semiconductive areas is provided in which conductive spacers may be formed to electrically connect the SOI areas to ground in order to overcome floating body effects that can occur with SOI. Additionally, insulative spacers may be formed on the surface of the conductive spacers to electrically isolate the SOI regions from the bulk regions. A novel method for making both of these products is provided in which the epitaxially grown, single crystalline bulk regions need not be selectively grown, because a sacrificial polishing layer is deposited, is also provided.

Abstract: A method of forming aluminum contacts of submicron dimensions wherein, after formation of both vias and line openings in a silicon oxide layer, a metal stop layer is deposited, followed by deposition of aluminum. Alternatively, the metal stop layer is deposited prior to forming the vias and line openings. The excess aluminum is removed by chemical-mechanical polishing, the stop layer providing high selectivity to the chemical mechanical polishing. The stop layer is then removed. The resultant silicon oxide-aluminum surface is planar and undamaged by the chemical-mechanical polishing step.

Abstract: A method of forming interlevel studs of at least two different materials in an insulating layer on a semiconductor wafer. After forming an insulating layer of BPSG on a Front End of the Line (FEOL) structure, the BPSG layer is chem-mech polished. Vias are formed through the BPSG layer in array areas. A thin doped poly layer is deposited on the surface of the BPSG layer. The structure is annealed and vias are formed in support areas. Dopants are implanted into support areas through the vias. After annealing to diffuse implanted dopant, a metal layer is formed on the poly layer. Then, the structure is chem-mech polished back to the poly layer. A final chem-mech polish step removes the poly layer, leaving metal studs in the support areas and poly-lined metal cored studs in the array areas.

Abstract: A method comprising the steps of: providing a substrate including an insulator material having a generally planar surface; forming a plurality of mesas of a semiconductor material on the substrate surface, the plurality of mesas spaced by channels extending to the substrate surface, the plurality of mesas including device mesas and dummy mesas; forming a polish-stop structure of at least one selected material over the substrate surface in the channels; polishing the plurality of mesas and stopping on the polish-stop structure whereby the plurality of mesas have the same thickness as the polish-stop structure; and replacing the dummy mesas with an insulator material whereby to electrically isolate the device mesas.

Abstract: Metallized semiconductor chips, such as are intended for VLSI, are coated with a first layer of SiO2 followed by a second layer of CVD diamond or DLC as an etch stop. The resulting structure is reproducibly and controllably planarized using a chem-mech slurry and an appropriate polishing pad, enabling subsequent layers to be built up similarly.

Abstract: A method for fabricating Josephson integrated circuits and the circuit is described incorporating the steps of depositing layers of different materials to form a trilayer Josephson junction, etching to define a plurality of trilayer areas, depositing dielectric material thereover, and chemical-mechanical polishing to planarize the dielectric material down to provide a coplanar surface with the tops of the trilayer areas for subsequent interconnection. The invention overcomes the problem of poor quality Josephson junctions, low Vm's, and crevices or gaps in the upper coplanar surface between the trilayer area and the surrounding dielectric material.