Patents by Inventor Mark A. Kassab
Mark A. Kassab has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Continuous application and decompression of test patterns and selective compaction of test responses
Patent number: 9664739Abstract: A method for applying test patterns to scan chains in a circuit-under-test. The method includes providing a compressed test pattern of bits; decompressing the compressed test pattern into a decompressed test pattern of bits as the compressed test pattern is being provided; and applying the decompressed test pattern to scan chains of the circuit-under-test. The actions of providing the compressed test pattern, decompressing the compressed test pattern, and applying the decompressed pattern are performed synchronously at the same or different clock rates, depending on the way in which the decompressed bits are to be generated. A circuit that performs the decompression includes a decompressor such as a linear finite state machine adapted to receive a compressed test pattern of bits. The decompressor decompresses the test pattern into a decompressed test pattern of bits as the compressed test pattern is being received.Type: GrantFiled: September 14, 2015Date of Patent: May 30, 2017Assignee: Mentor Graphics CorporationInventors: Janusz Rasjki, Jerzy Tyszer, Mark Kassab, Nilanjan Mukherjee -
Patent number: 9651622Abstract: Various aspects of the disclosed technology relate to techniques of creating test templates for test pattern generation. Residual test cubes for a plurality of faults are first generated based on a signal probability analysis of a circuit design. Test templates are then generated based on merging the residual test cubes. Finally, a plurality of test patterns and/or compressed test cubes are generated based on one of the test templates.Type: GrantFiled: March 9, 2015Date of Patent: May 16, 2017Assignee: Mentor Graphics CorporationInventors: Janusz Rajski, Amit Kumar, Mark A. Kassab, Elham Moghaddam, Nilanjan Mukherjee, Jerzy Tyszer, Chen Wang
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Publication number: 20160320450Abstract: Disclosed herein are exemplary embodiments of a so-called “X-press” test response compactor. Certain embodiments of the disclosed compactor comprise an overdrive section and scan chain selection logic. Certain embodiments of the disclosed technology offer compaction ratios on the order of 1000×. Exemplary embodiments of the disclosed compactor can maintain about the same coverage and about the same diagnostic resolution as that of conventional scan-based test scenarios. Some embodiments of a scan chain selection scheme can significantly reduce or entirely eliminate unknown states occurring in test responses that enter the compactor. Also disclosed herein are embodiments of on-chip comparator circuits and methods for generating control circuitry for masking selection circuits.Type: ApplicationFiled: February 1, 2016Publication date: November 3, 2016Applicant: Mentor Graphics CorporationInventors: Janusz Rajski, Jerzy Tyszer, Grzegorz Mrugalski, Mark Kassab, Wu-Tung Cheng
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Patent number: 9335374Abstract: Various aspects of the disclosed techniques relate to using dynamic shift for test pattern compression. Scan chains are divided into segments. Non-shift clock cycles are added to one or more segments to make an uncompressible test pattern compressible. The one or more segments may be selected based on compressibility, the number of specified bits and/or the location on the scan chains. A dynamic shift controller may be employed to control the dynamic shift.Type: GrantFiled: December 2, 2014Date of Patent: May 10, 2016Assignee: Mentor Graphics CorporationInventors: Xijiang Lin, Mark A. Kassab, Janusz Rajski
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CONTINUOUS APPLICATION AND DECOMPRESSION OF TEST PATTERNS AND SELECTIVE COMPACTION OF TEST RESPONSES
Publication number: 20160003907Abstract: A method for applying test patterns to scan chains in a circuit-under-test. The method includes providing a compressed test pattern of bits; decompressing the compressed test pattern into a decompressed test pattern of bits as the compressed test pattern is being provided; and applying the decompressed test pattern to scan chains of the circuit-under-test. The actions of providing the compressed test pattern, decompressing the compressed test pattern, and applying the decompressed pattern are performed synchronously at the same or different clock rates, depending on the way in which the decompressed bits are to be generated. A circuit that performs the decompression includes a decompressor such as a linear finite state machine adapted to receive a compressed test pattern of bits. The decompressor decompresses the test pattern into a decompressed test pattern of bits as the compressed test pattern is being received.Type: ApplicationFiled: September 14, 2015Publication date: January 7, 2016Applicant: Mentor Graphics CorporationInventors: Janusz Rasjki, Jerzy Tyszer, Mark Kassab, Nilanjan Mukherjee -
Publication number: 20150323600Abstract: Disclosed herein are exemplary methods, apparatus, and systems for performing timing-aware automatic test pattern generation (ATPG) that can be used, for example, to improve the quality of a test set generated for detecting delay defects or holding time defects. In certain embodiments, timing information derived from various sources (e.g. from Standard Delay Format (SDF) files) is integrated into an ATPG tool. The timing information can be used to guide the test generator to detect the faults through certain paths (e.g., paths having a selected length, or range of lengths, such as the longest or shortest paths). To avoid propagating the faults through similar paths repeatedly, a weighted random method can be used to improve the path coverage during test generation. Experimental results show that significant test quality improvement can be achieved when applying embodiments of timing-aware ATPG to industrial designs.Type: ApplicationFiled: July 20, 2015Publication date: November 12, 2015Applicant: MENTOR GRAPHICS CORPORATIONInventors: Xijiang Lin, Kun-Han Tsai, Mark Kassab, Chen Wang, Janusz Rajski
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Publication number: 20150285854Abstract: Disclosed are representative embodiments of methods, apparatus, and systems for test scheduling and test access in a test compression environment. Clusters of test patterns for testing a plurality of cores in a circuit are formed based on test information that includes compressed test data, corresponding tester channel requirements and correlated cores. The formation of test pattern clusters is followed by tester channel allocation. A best-fit scheme or a balanced-fit scheme may be employed to generate channel allocation information. A test access circuit for dynamic channel allocation can be designed based on the channel allocation information.Type: ApplicationFiled: March 16, 2011Publication date: October 8, 2015Inventors: Mark A. Kassab, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Jakub Janicki, Tyszer Jerzy
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Continuous application and decompression of test patterns and selective compaction of test responses
Patent number: 9134370Abstract: A method for applying test patterns to scan chains in a circuit-under-test. The method includes providing a compressed test pattern of bits; decompressing the compressed test pattern into a decompressed test pattern of bits as the compressed test pattern is being provided; and applying the decompressed test pattern to scan chains of the circuit-under-test. The actions of providing the compressed test pattern, decompressing the compressed test pattern, and applying the decompressed pattern are performed synchronously at the same or different clock rates, depending on the way in which the decompressed bits are to be generated. A circuit that performs the decompression includes a decompressor such as a linear finite state machine adapted to receive a compressed test pattern of bits. The decompressor decompresses the test pattern into a decompressed test pattern of bits as the compressed test pattern is being received.Type: GrantFiled: September 9, 2013Date of Patent: September 15, 2015Assignee: Mentor Graphics CorporationInventors: Janusz Rajski, Jerzy Tyszer, Mark Kassab, Nilanjan Mukherjee -
Publication number: 20150253385Abstract: Various aspects of the disclosed technology relate to techniques of creating test templates for test pattern generation. Residual test cubes for a plurality of faults are first generated based on a signal probability analysis of a circuit design. Test templates are then generated based on merging the residual test cubes. Finally, a plurality of test patterns and/or compressed test cubes are generated based on one of the test templates.Type: ApplicationFiled: March 9, 2015Publication date: September 10, 2015Inventors: Janusz Rajski, Amit Kumar, Mark A. Kassab, Elham Moghaddam, Nilanjan Mukherjee, Jerzy Tyszer, Chen Wang
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Patent number: 9088522Abstract: Disclosed are representative embodiments of methods, apparatus, and systems for test scheduling for testing a plurality of cores in a system on circuit. Test data are encoded to derive compressed test patterns that require small numbers of core input channels. Core input/output channel requirement information for each of the compressed test patterns is determined accordingly. The compressed patterns are grouped into test pattern classes. The formation of the test pattern classes is followed by allocation circuit input and output channels and test application time slots that may comprise merging complementary test pattern classes into clusters that can work with a particular test access mechanism. The test access mechanism may be designed independent of the test data.Type: GrantFiled: January 17, 2012Date of Patent: July 21, 2015Assignee: Mentor Graphics CorporationInventors: Janusz Rajski, Mark A Kassab, Grzegorz Mrugalski, Nilanjan Mukherjee, Jakub Janicki, Jerzy Tyszer, Avijit Dutta
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Patent number: 9086454Abstract: Disclosed herein are exemplary methods, apparatus, and systems for performing timing-aware automatic test pattern generation (ATPG) that can be used, for example, to improve the quality of a test set generated for detecting delay defects or holding time defects. In certain embodiments, timing information derived from various sources (e.g. from Standard Delay Format (SDF) files) is integrated into an ATPG tool. The timing information can be used to guide the test generator to detect the faults through certain paths (e.g., paths having a selected length, or range of lengths, such as the longest or shortest paths). To avoid propagating the faults through similar paths repeatedly, a weighted random method can be used to improve the path coverage during test generation. Experimental results show that significant test quality improvement can be achieved when applying embodiments of timing-aware ATPG to industrial designs.Type: GrantFiled: October 14, 2013Date of Patent: July 21, 2015Assignee: Mentor Graphics CorporationInventors: Xijiang Lin, Kun-Han Tsai, Mark Kassab, Chen Wang, Janusz Rajski
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Publication number: 20150153410Abstract: Various aspects of the disclosed techniques relate to using dynamic shift for test pattern compression. Scan chains are divided into segments. Non-shift clock cycles are added to one or more segments to make an uncompressible test pattern compressible. The one or more segments may be selected based on compressibility, the number of specified bits and/or the location on the scan chains. A dynamic shift controller may be employed to control the dynamic shift.Type: ApplicationFiled: December 2, 2014Publication date: June 4, 2015Inventors: Xijiang Lin, Mark A. Kassab, Janusz Rajski
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Publication number: 20150149847Abstract: Various aspects of the disclosed techniques relate to channel sharing techniques for testing circuits having non-identical cores. Compressed test patterns for a plurality of circuit blocks are generated for channel sharing. Each of the plurality of circuit blocks comprises a decompressor configured to decompress the compressed test patterns. Test data input channels are thus shared by the decompressors. Control data input channels are usually not shared by non-identical circuit blocks in the plurality of circuit blocks.Type: ApplicationFiled: November 26, 2014Publication date: May 28, 2015Inventors: Yu Huang, Mark A. Kassab, Janusz Rajski, Wu-Tung Cheng, Jay Babak Jahangiri
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Patent number: 9026874Abstract: Disclosed are representative embodiments of methods, apparatus, and systems for partitioning-based Test Access Mechanisms (TAM). Test response data are captured by scan cells of a plurality scan chains in a circuit under test and are compared with test response data expected for a good CUT to generate check values. Based on the check values, partition pass/fail signals are generated by partitioning scheme generators. Each of the partitioning scheme generators is configured to generate one of the partition pass/fail signals for one of partitioning schemes. A partitioning scheme divides the scan cells into a set of non-overlapping partitions. Based on the partition pass/fail signals, a failure diagnosis process may be performed.Type: GrantFiled: December 9, 2013Date of Patent: May 5, 2015Assignee: Mentor Graphics CorporationInventors: Wu-Tung Cheng, Manish Sharma, Avijit Dutta, Robert Brady Benware, Mark A. Kassab
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Patent number: 8726112Abstract: Methods and devices for using high-speed serial links for scan testing are disclosed. The methods can work with any scheme of scan data compression or with uncompressed scan testing. The protocol and hardware to support high speed data transfer reside on both the tester and the device under test. Control data may be transferred along with scan data or be partially generated on chip. Clock signals for testing may be generated on chip as well. In various implementations, the SerDes (Serializer/Deserializer) may be shared with other applications. The Aurora Protocol may be used to transport industry standard protocols. To compensate for effects of asynchronous operation of a conventional high-speed serial link, buffers may be used. The high-speed serial interface may use a data conversion block to drive test cores.Type: GrantFiled: July 20, 2009Date of Patent: May 13, 2014Assignee: Mentor Graphics CorporationInventors: Janusz Rajski, Nilanjan Mukherjee, Mark A Kassab, Thomas H. Rinderknecht, Mohamed Dessouky
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Publication number: 20140101506Abstract: Disclosed are representative embodiments of methods, apparatus, and systems for partitioning-based Test Access Mechanisms (TAM). Test response data are captured by scan cells of a plurality scan chains in a circuit under test and are compared with test response data expected for a good CUT to generate check values. Based on the check values, partition pass/fail signals are generated by partitioning scheme generators. Each of the partitioning scheme generators is configured to generate one of the partition pass/fail signals for one of partitioning schemes. A partitioning scheme divides the scan cells into a set of non-overlapping partitions. Based on the partition pass/fail signals, a failure diagnosis process may be performed.Type: ApplicationFiled: December 9, 2013Publication date: April 10, 2014Applicant: MENTOR GRAPHICS CORPORATIONInventors: Wu-Tung Cheng, Manish Sharma, Avijit Dutta, Robert Brady Benware, Mark A. Kassab
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Publication number: 20140047404Abstract: Disclosed herein are exemplary methods, apparatus, and systems for performing timing-aware automatic test pattern generation (ATPG) that can be used, for example, to improve the quality of a test set generated for detecting delay defects or holding time defects. In certain embodiments, timing information derived from various sources (e.g. from Standard Delay Format (SDF) files) is integrated into an ATPG tool. The timing information can be used to guide the test generator to detect the faults through certain paths (e.g., paths having a selected length, or range of lengths, such as the longest or shortest paths). To avoid propagating the faults through similar paths repeatedly, a weighted random method can be used to improve the path coverage during test generation. Experimental results show that significant test quality improvement can be achieved when applying embodiments of timing-aware ATPG to industrial designs.Type: ApplicationFiled: October 14, 2013Publication date: February 13, 2014Applicant: Mentor Graphics CorporationInventors: Xijiang Lin, Kun-Han Tsai, Mark Kassab, Chen Wang, Janusz Rajski
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CONTINUOUS APPLICATION AND DECOMPRESSION OF TEST PATTERNS AND SELECTIVE COMPACTION OF TEST RESPONSES
Publication number: 20140006888Abstract: A method for applying test patterns to scan chains in a circuit-under-test. The method includes providing a compressed test pattern of bits; decompressing the compressed test pattern into a decompressed test pattern of bits as the compressed test pattern is being provided; and applying the decompressed test pattern to scan chains of the circuit-under-test. The actions of providing the compressed test pattern, decompressing the compressed test pattern, and applying the decompressed pattern are performed synchronously at the same or different clock rates, depending on the way in which the decompressed bits are to be generated. A circuit that performs the decompression includes a decompressor such as a linear finite state machine adapted to receive a compressed test pattern of bits. The decompressor decompresses the test pattern into a decompressed test pattern of bits as the compressed test pattern is being received.Type: ApplicationFiled: September 9, 2013Publication date: January 2, 2014Applicant: MENTOR GRAPHICS CORPORATIONInventors: Janusz Rajski, Jerzy Tyszer, Mark Kassab, Nilanjan Mukherjee -
Patent number: 8607107Abstract: Disclosed are representative embodiments of methods, apparatus, and systems for partitioning-based Test Access Mechanisms (TAM). Test response data are captured by scan cells of a plurality scan chains in a circuit under test and are compared with test response data expected for a good CUT to generate check values. Based on the check values, partition pass/fail signals are generated by partitioning scheme generators. Each of the partitioning scheme generators is configured to generate one of the partition pass/fail signals for one of partitioning schemes. A partitioning scheme divides the scan cells into a set of non-overlapping partitions. Based on the partition pass/fail signals, a failure diagnosis process may be performed.Type: GrantFiled: April 20, 2011Date of Patent: December 10, 2013Assignee: Mentor Graphics CorporationInventors: Wu-Tung Cheng, Manish Sharma, Avijit Dutta, Robert Brady Benware, Mark A Kassab
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Publication number: 20130290795Abstract: Disclosed are representative embodiments of methods, apparatus, and systems for test scheduling for testing a plurality of cores in a system on circuit. Test data are encoded to derive compressed test patterns that require small numbers of core input channels. Core input/output channel requirement information for each of the compressed test patterns is determined accordingly. The compressed patterns are grouped into test pattern classes. The formation of the test pattern classes is followed by allocation circuit input and output channels and test application time slots that may comprise merging complementary test pattern classes into clusters that can work with a particular test access mechanism. The test access mechanism may be designed independent of the test data.Type: ApplicationFiled: January 17, 2012Publication date: October 31, 2013Applicant: Mentor Graphics CorporationInventors: Janusz Rajski, Mark A. Kassab, Grzegorz Mrugalski, Nilanjan Mukherjee, Jakub Janicki, Jerzy Tyszer, Avijit Dutta