Patents by Inventor Mark A. Lancaster

Mark A. Lancaster has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10020094
    Abstract: An electric conductor may be provided. The electric conductor may comprise a conductor core and a plurality of conductor strands wrapped around the conductor core. The conductor core may comprise a plurality of core strands comprising an overall number of strands. The plurality of core strands may comprise a first portion of core strands and a second portion of core strands. The first portion of core strands may comprise a first number of strands. The first portion of core strands may comprise steel. The second portion of core strands may comprise a second number of strands. The second portion of core strands may comprise a composite material. A ratio of the first number of strands to the overall number of strands and a ratio of the second number of strands to the overall number of strands may be optimized to give the conductor core a predetermined characteristic.
    Type: Grant
    Filed: October 10, 2016
    Date of Patent: July 10, 2018
    Assignee: Southwire Company, LLC
    Inventor: Mark A. Lancaster
  • Patent number: 9634681
    Abstract: The embodiments described herein provide analog-to-digital converters (ADCs) and systems and methods for calibrating ADCs, including ADCs with poorly characterized nonlinearities that cannot be effectively calibrated with traditional calibration techniques. In general, the embodiments described herein calibrate by measuring output values from an ADC with a known calibration input values being applied. The measured output values are used to determine localized polynomial interpolants. Each of the determined localized polynomial interpolants is then evaluated at an uncorrected output value, and the evaluated localized polynomial interpolants are then used to generate correction values. These correction values can then be used to calibrate the ADC during later operation. Such a calibration technique can provide effective calibration for a variety of ADCs, including ADCs that use inverter-based voltage-to-current (VI) converters and current-controlled ring oscillators.
    Type: Grant
    Filed: July 27, 2016
    Date of Patent: April 25, 2017
    Assignee: NXP USA, Inc.
    Inventors: George R. Kunnen, Mark A. Lancaster
  • Publication number: 20170025202
    Abstract: An electric conductor may be provided. The electric conductor may comprise a conductor core and a plurality of conductor strands wrapped around the conductor core. The conductor core may comprise a plurality of core strands comprising an overall number of strands. The plurality of core strands may comprise a first portion of core strands and a second portion of core strands. The first portion of core strands may comprise a first number of strands. The first portion of core strands may comprise steel. The second portion of core strands may comprise a second number of strands. The second portion of core strands may comprise a composite material. A ratio of the first number of strands to the overall number of strands and a ratio of the second number of strands to the overall number of strands may be optimized to give the conductor core a predetermined characteristic.
    Type: Application
    Filed: October 10, 2016
    Publication date: January 26, 2017
    Inventor: Mark A. Lancaster
  • Patent number: 9548753
    Abstract: The embodiments described herein provide calibration systems and methods for mixed-signal devices. Specifically, the embodiments provide systems and methods for calibrating mixed-signal devices that can facilitate effective calibration of such mixed-signal devices, including mixed-signal devices with poorly characterized nonlinearities that cannot be effectively calibrated with traditional calibration techniques. In general, the embodiments described herein calibrate by measuring output values from a mixed-signal device with a known calibration input values being applied. The measured output values are used to determine localized polynomial interpolants. Each of the determined localized polynomial interpolants is then evaluated at an uncorrected output value, and the evaluated localized polynomial interpolants are then used to generate correction values.
    Type: Grant
    Filed: July 27, 2016
    Date of Patent: January 17, 2017
    Assignee: NXP USA, Inc.
    Inventors: George R. Kunnen, Mark A. Lancaster
  • Patent number: 9490050
    Abstract: An electric conductor may be provided. The electric conductor may comprise a conductor core and a plurality of conductor strands wrapped around the conductor core. The conductor core may comprise a plurality of core strands comprising an overall number of strands. The plurality of core strands may comprise a first portion of core strands and a second portion of core strands. The first portion of core strands may comprise a first number of strands. The first portion of core strands may comprise steel. The second portion of core strands may comprise a second number of strands. The second portion of core strands may comprise a composite material. A ratio of the first number of strands to the overall number of strands and a ratio of the second number of strands to the overall number of strands may be optimized to give the conductor core a predetermined characteristic.
    Type: Grant
    Filed: March 11, 2014
    Date of Patent: November 8, 2016
    Assignee: Southwire Company, LLC
    Inventor: Mark A. Lancaster
  • Patent number: 9219493
    Abstract: A system includes an analog-to-digital converter (ADC) for converting an analog input signal to a digital signal output and a nonlinearity corrector for correcting nonlinear error in the digital signal output to produce a corrected digital signal output. A source of the nonlinear error is associated with the ADC, wherein an analog calibration signal is introduced to the source of the nonlinear error during conversion of the analog calibration signal to a digital calibration output having the nonlinear error. After conversion of the analog calibration signal to the digital calibration output, a calibration circuit calculates expected values of correlation sums in response to the digital calibration output and determines correction coefficients using the expected values of the correlation sums. The calibration circuit provides correction data based upon the correction coefficients to the nonlinearity corrector.
    Type: Grant
    Filed: November 21, 2014
    Date of Patent: December 22, 2015
    Assignee: Freesscale Semiconductor, Inc.
    Inventors: George R. Kunnen, Mark A. Lancaster
  • Publication number: 20150256165
    Abstract: A system and method are present for generating a modulated waveform. A timer is configured to generate a first modulated waveform signal, and an adder module is configured to calculate a delay. The delay includes at least one of an edge fractional delay and a dead time fractional delay. A delay module is operably coupled to the timer and the adder module. The delay module is configured to delay at least one of a rising edge of the first modulated waveform signal and a falling edge of the first modulated waveform signal by the delay to generate a second modulated waveform signal that has a higher frequency resolution than a frequency resolution of the first modulated waveform signal.
    Type: Application
    Filed: March 6, 2014
    Publication date: September 10, 2015
    Applicant: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Mark A. Lancaster, Chongli Wu
  • Patent number: 9118311
    Abstract: A system and method are present for generating a modulated waveform. A timer is configured to generate a first modulated waveform signal, and an adder module is configured to calculate a delay. The delay includes at least one of an edge fractional delay and a dead time fractional delay. A delay module is operably coupled to the timer and the adder module. The delay module is configured to delay at least one of a rising edge of the first modulated waveform signal and a falling edge of the first modulated waveform signal by the delay to generate a second modulated waveform signal that has a higher frequency resolution than a frequency resolution of the first modulated waveform signal.
    Type: Grant
    Filed: March 6, 2014
    Date of Patent: August 25, 2015
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Mark A. Lancaster, Chongli Wu
  • Publication number: 20140251653
    Abstract: An electric conductor may be provided. The electric conductor may comprise a conductor core and a plurality of conductor strands wrapped around the conductor core. The conductor core may comprise a plurality of core strands comprising an overall number of strands. The plurality of core strands may comprise a first portion of core strands and a second portion of core strands. The first portion of core strands may comprise a first number of strands. The first portion of core strands may comprise steel. The second portion of core strands may comprise a second number of strands. The second portion of core strands may comprise a composite material. A ratio of the first number of strands to the overall number of strands and a ratio of the second number of strands to the overall number of strands may be optimized to give the conductor core a predetermined characteristic.
    Type: Application
    Filed: March 11, 2014
    Publication date: September 11, 2014
    Applicant: Southwire Company, LLC
    Inventor: Mark A. Lancaster
  • Patent number: 7916053
    Abstract: Apparatus and methods are provided for performing a sampling sequence for a plurality of samples. An analog-to-digital conversion module comprises a sampling module, a register, and a sampling control module coupled to the sampling module and the register. The sampling module is configured to convert analog signals into corresponding digital values in response to sampling trigger signals and the register is configured to maintain scan mode criteria for a plurality of samples. The sampling control module is configured to identify a scan mode criterion for a respective sample of the plurality of samples, automatically generate a sampling trigger signal when the scan mode criterion for the respective sample is equal to a first value, and generate the sampling trigger signal in response to a timing trigger signal when the scan mode criterion for the respective sample is equal to a second value.
    Type: Grant
    Filed: March 30, 2009
    Date of Patent: March 29, 2011
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Michael E. Stanley, Mark A. Lancaster, Chongli Wu
  • Publication number: 20100245143
    Abstract: Apparatus and methods are provided for performing a sampling sequence for a plurality of samples. An analog-to-digital conversion module comprises a sampling module, a register, and a sampling control module coupled to the sampling module and the register. The sampling module is configured to convert analog signals into corresponding digital values in response to sampling trigger signals and the register is configured to maintain scan mode criteria for a plurality of samples. The sampling control module is configured to identify a scan mode criterion for a respective sample of the plurality of samples, automatically generate a sampling trigger signal when the scan mode criterion for the respective sample is equal to a first value, and generate the sampling trigger signal in response to a timing trigger signal when the scan mode criterion for the respective sample is equal to a second value.
    Type: Application
    Filed: March 30, 2009
    Publication date: September 30, 2010
    Applicant: Freescale Semiconductor, Inc.
    Inventors: Michael E. Stanley, Mark A. Lancaster, Chongli Wu