Abstract: Disclosed is a circuit which selects one of the elements of a translation lookaside buffer for replacement while excluding all other elements that are eligible for replacement. The circuit divides the entries into major groups and further sub-divides each major group into minor groups of elements. Each element within each minor group examines the previous major group, the previous minor group, and the previous entry within the minor group to determine whether an element has already been selected. The circuit will select an entry only if no previous entry within the minor group has been selected, no previous minor group has been selected, and no previous major group has been selected.

Abstract: Disclosed is an apparatus and method which combines the mask information with the virtual page number in each block entry of a translation lookaside buffer of a virtual memory system. The invention defines a range of pages that are translated by a block entry, thus providing space in the virtual page number for the mask bits. The mask information is duplicated in the real page number of the block entry that corresponds to the virtual page number. This duplication allows the mask information to be easily sent to the bus driver circuits where it is needed to select the bits that form the real page number.

Abstract: A complementary metal oxide semiconductor (CMOS) inverter circuit wherein the complementary PFET is replaced by a small CMOS inverter and an NFET having a size substantially the same as that of the complementary NFET. By so adding the small CMOS inverter and changing the complementary PFET to an NFET, power may be reduced and speed increased. Such an inverter is preferably used in a latching bus receiver to reduce setup time. This is made possible due to the characteristics of an NFET relative to those of a PFET, namely, that the NFET changes logic level much more quickly than a correspondingly sized PFET. These circuits may also be used for decreasing the high to low and low to high setup times for latching purposes. A faster input to output latching speed is thus made possible without increasing the power even for heavily loaded outputs, and all of this may be done with a similar utilization of chip area.