Patents by Inventor Mark A. Moran

Mark A. Moran has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7853811
    Abstract: An integrated circuit (300) includes a suspend circuit that includes a first input to receive a suspend signal, a first output to generate an awake signal, and outputs to provide control signals to various integrated circuit resources. During suspend mode, the suspend circuit suspends operation of the integrated circuit resources by driving its output pins to one of a plurality of predefined state selected by corresponding mode select signals and by locking its synchronous elements to known states. Upon termination of suspend mode, the circuit re-activates the integrated circuit resources according to a user-defined timing schedule. The user-defined timing schedule and the mode select signals may be provided to the integrated circuit during its configuration as part of a configuration bitstream.
    Type: Grant
    Filed: August 3, 2006
    Date of Patent: December 14, 2010
    Assignee: Xilinx, Inc.
    Inventors: James A. Walstrum, Jr., Mark A. Moran, Jinsong Oliver Huang, Patrick J. Crotty
  • Patent number: 5452229
    Abstract: A non-volatile, in-system programmable integrated-circuit switch has horizontal conductive lines and vertical conductive lines. A programmable interconnect cell including a floating gate transistor is provided at each intersection of a horizontal line and a vertical line. Each line is connected to a pin through a programmable I/O cell which includes a floating gate transistor. Each I/O cell can be programmed to configure the corresponding pin as an input pin or as an inverting or non-inverting output pin. The I/O cell can also be programmed to tri-state the pin or to fix the pin at a high or low voltage level. Each input pin can be connected to more than one output pins. A TTL-to-CMOS translator in each I/O cell is provided in the output section of the cell to reduce the translator output load and make the load, and hence the speed and power consumption of the switch, less dependent on the switch programming.
    Type: Grant
    Filed: December 18, 1992
    Date of Patent: September 19, 1995
    Assignee: Lattice Semiconductor Corporation
    Inventors: Kapil Shankar, Mark A. Moran, Thomas J. Davies, Jr.