Abstract: An unchecked signal detection mechanism runs simulation tests of circuit designs that normally pass. Before a simulation test is run, noise is injected into one randomly chosen signal. A random constant value is assigned to the randomly chosen signal. The constant random value is forced on the selected signal for the duration of the simulation test. Signals for which simulation tests always pass, even when their value is forced, are likely not checked and declared as suspect. The subset of suspect signals is then checked to determine whether their checkers are indeed missing or defective. Any verification flaws (holes) found are then fixed.

Abstract: An unchecked signal detection mechanism runs simulation tests of circuit designs that normally pass. Before a simulation test is run, noise is injected into one randomly chosen signal. A random constant value is assigned to the randomly chosen signal. The constant random value is forced on the selected signal for the duration of the simulation test. Signals for which simulation tests always pass, even when their value is forced, are likely not checked and declared as suspect. The subset of suspect signals is then checked to determine whether their checkers are indeed missing or defective. Any verification flaws (holes) found are then fixed.