Abstract: An example non-transitory machine-readable storage medium storing machine-readable instructions which when executed cause a processor to obtain stored bits stored on a flash memory, each of the stored bits in a set state or an unset state. The processor further obtains target bits, each of the target bits in the set state or the unset state, wherein each target bit corresponds to a stored bit to update the stored bit. The processor further determines whether, for one stored bit in the set state, the corresponding target bit is in the unset state. When the determination is positive, the processor sets the stored bits to the unset state and, after setting the stored bits to the unset state, updates the stored bits to match the corresponding target bits. When the determination is negative, the processor updates the stored bits to match the corresponding target bits.

Abstract: An example of an apparatus is provided. The apparatus includes a power supply to connect to a power source. The power supply is to receive and to distribute a total power from the power source. The apparatus further includes a first device to receive a first portion of the total power from the power supply. The apparatus further includes a second device to receive a second portion of the total power from the power supply. A sum of the first portion and the second portion is the total power. In addition, the apparatus includes a controller to control the second device, wherein the controller is to determine the total power demanded by the first device and the second device. The controller is to reduce the second portion of the total power and to restore the second portion of the total power.

Abstract: An example non-transitory machine-readable storage medium storing machine-readable instructions which when executed cause a processor to obtain stored bits stored on a flash memory, each of the stored bits in a set state or an unset state. The processor further obtains target bits, each of the target bits in the set state or the unset state, wherein each target bit corresponds to a stored bit to update the stored bit. The processor further determines whether, for one stored bit in the set state, the corresponding target bit is in the unset state. When the determination is positive, the processor sets the stored bits to the unset state and, after setting the stored bits to the unset state, updates the stored bits to match the corresponding target bits. When the determination is negative, the processor updates the stored bits to match the corresponding target bits.

Abstract: An example of an apparatus is provided. The apparatus includes a power supply to connect to a power source. The power supply is to receive and to distribute a total power from the power source. The apparatus further includes a first device to receive a first portion of the total power from the power supply. The apparatus further includes a second device to receive a second portion of the total power from the power supply. A sum of the first portion and the second portion is the total power. In addition, the apparatus includes a controller to control the second device, wherein the controller is to determine the total power demanded by the first device and the second device. The controller is to reduce the second portion of the total power and to restore the second portion of the total power.

Abstract: A circuit for identifying a power supply may include a voltage divider to divide an identification voltage from the power supply. The output of the voltage divider is electrically coupled to an adapter identification pin of a controller to identify the power supply.

Abstract: Example systems relate to power monitoring and reduction processes. An example system may include a modular computing device including a plurality of universal serial bus (USB) ports and a power supply unit coupled to the modular computing device. The example system may further include an embedded controller coupled to the power supply unit and to the plurality of USB port. The embedded controller may monitor a level of power consumed by the system and determine whether a surge event has occurred in the system. In response to the determination that the surge event has occurred, the embedded controller may determine whether an agency event has occurred in the system and initiate a power reduction process in response to the determination.

Abstract: An apparatus may include a basic input/output system (BIOS) coupled to a controller. A communication port may be coupled to the controller. The controller may determine that the communication port has entered a locked state, send a first signal to the communication port to power off a bus associated with the communication port for a threshold period of time, and send a second signal to the communication port to power on the bus associated with the communication port in response to expiration of the threshold period of time.

Abstract: Example implementations relate to assigning power sources. An example system includes a network device and a computing device with a BIOS. The BIOS provides the network device a heartbeat in response to the computing device entering a hibernation state, assigns a power source to a network interface card (NIC) of the network device via a power delivery controller, and assigns the NIC to receive Wake-On-Lan (WOL) support. The system can place the computing device to a threshold power state responsive to the NIC receiving WOL support.

Abstract: Example implementations relate to balancing a power load among USB ports. For example, an apparatus according to the present disclosure, may include a plurality of USB ports, and an embedded controller coupled to the plurality of USB ports. The embedded controller may determine that a first device is coupled to a USB port of the plurality of USB ports, and determine a power draw of the first device relative to a type of the USB port. The embedded controller may balance a power load among a remainder of the plurality of USB ports based on the power draw of the first device relative to the type of the USB port.

Abstract: In some examples, a protected memory area inaccessible to an operating system stores information relating to instructions, where the protected memory area includes an indication settable to a first value to indicate that the instructions are allowed to access a memory external of the protected memory area, and a second value to indicate that the instructions are not allowed to access the memory external of the protected memory area. The indication is modified from the first value to the second value to restrict the instructions when executed from accessing the memory external of the protected memory area. In response to modifying the indication, code in the computing device is launched, the launched code comprising the operating system or firmware.

Abstract: According to examples, an apparatus may include a power circuit to transmit standby power to a device, a memory associated with the device to maintain first configuration data and second configuration data and a battery to provide backup power to the device. The device may, following a loss and a recovery of the standby power to the device, determine whether the backup power was lost during the loss of the standby power. The device may also, based on a determination that the backup power was lost during the loss of the standby power, read the first configuration data or may, based on a determination that the backup power was not lost during the loss of the standby power, read the second configuration data. The device may further apply the read one of the first configuration data or the second configuration data to configure the device.

Abstract: Examples associated with basic input/output system (BIOS) up-dates are described. One example method includes system management mode locking a first pre-extensible firmware interface initialization (PEI) region and a driver execution environment (DXE) region of a shared serial peripheral (SPI) chip of a BIOS of a computer. A second PEI region of the shared SPI chip is chipset locked. A record in a system management random access memory associated with a video option read only memory (ROM) is created. The video option ROM is loaded. The first PEI region is updated, and periodic graphical updates regarding the progress of updating the first PEI region are provided using the video option ROM.

Abstract: A circuit for identifying a power supply may include a voltage divider to divide an identification voltage from the power supply. The output of the voltage divider is electrically coupled to an adapter identification pin of a controller to identify the power supply.

Abstract: According to examples, an apparatus may include a power circuit to transmit standby power to a device, a memory associated with the device to maintain first configuration data and second configuration data and a battery to provide backup power to the device. The device may, following a loss and a recovery of the standby power to the device, determine whether the backup power was lost during the loss of the standby power. The device may also, based on a determination that the backup power was lost during the loss of the standby power, read the first configuration data or may, based on a determination that the backup power was not lost during the loss of the standby power, read the second configuration data. The device may further apply the read one of the first configuration data or the second configuration data to configure the device.

Abstract: An apparatus may include a basic input/output system (BIOS) coupled to a controller. A communication port may be coupled to the controller. The controller may determine that the communication port has entered a locked state, send a first signal to the communication port to power off a bus associated with the communication port for a threshold period of time, and send a second signal to the communication port to power on the bus associated with the communication port in response to expiration of the threshold period of time.

Abstract: An example system includes a processor. The system also includes a peripheral interface that includes a controller communicatively coupled to the processor. The controller is to request information from a plurality of devices connected to the peripheral interface prior to the processor requesting the information. The controller is to provide the information to the processor.

Abstract: Example implementations relate to balancing a power load among USB ports. For example, an apparatus according to the present disclosure, may include a plurality of USB ports, and an embedded controller coupled to the plurality of USB ports. The embedded controller may determine that a first device is coupled to a USB port of the plurality of USB ports, and determine a power draw of the first device relative to a type of the USB port. The embedded controller may balance a power load among a remainder of the plurality of USB ports based on the power draw of the first device relative to the type of the USB port.

Abstract: Example systems relate to power monitoring and reduction processes. An example system may include a modular computing device including a plurality of universal serial bus (USB) ports and a power supply unit coupled to the modular computing device. The example system may further include an embedded controller coupled to the power supply unit and to the plurality of USB port. The embedded controller may monitor a level of power consumed by the system and determine whether a surge event has occurred in the system. In response to the determination that the surge event has occurred, the embedded controller may determine whether an agency event has occurred in the system and initiate a power reduction process in response to the determination.

Abstract: Examples of an apparatus, method, and instructions included on a machine-readable non-transitory storage medium are disclosed herein. In an example of the method, a first state is provided to enable a camera to record an image, a second state is provided to disable the camera, and a third state is provided to permit the camera to be enabled and disabled. Also in this example of the method, a button is actuated in the third state to an on position to enable the camera to record an image or an off position to disable the camera. Additionally in this example of the method, a signal is generated via an input device in the on position of the button to enable the camera to record an image or disable the camera.

Abstract: In some examples, a protected memory area inaccessible to an operating system stores information relating to instructions, where the protected memory area includes an indication settable to a first value to indicate that the instructions are allowed to access a memory external of the protected memory area, and a second value to indicate that the instructions are not allowed to access the memory external of the protected memory area. The indication is modified from the first value to the second value to restrict the instructions when executed from accessing the memory external of the protected memory area. In response to modifying the indication, code in the computing device is launched, the launched code comprising the operating system or firmware.